Senior DFT Engineer

Prodapt ASIC services (formerly Innovative Logic) is the leading provider of SoC ASIC/FPGA and Embedded Software services. Our business model is to offer our services based on turnkey, Offshore design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Embedded services: device drivers, RTOS porting, Board bring up. Prodapt is looking for a Senior DFT Engineer who has recent experience working on complex SoCs using JTAG, Scan, memory BIST, scan compression, ATPG vector generation, Mentor/Siemens Tessent Boundary Scan, and DFT for mixed-signal and digital IpsLocation: El Segundo, CA/Mountain View, CAResponsibilitiesWhat you’ll be doing: Implement DFT methodologies and designs including JTAG, Scan, and Memory BIST and Mentor/Siemens Tessent at module and chip levels. Work closely with designers to enable designs to be DFT-friendly on modules and sub-systems. Help identify and fix design issues to enable smooth DFT implementation. Collaborate with physical implementation engineers and ASIC vendors in implementing DFT features for Automotive grade silicon. Collaborate with designers to run Synthesis on modules and sub-systems, and identify and fix RTL, timing and implementation issues. Work closely with 3rd party IP vendors on proper DFT implementation for the IPs Define test structures, debug structures and test plans. Create test vectors, simulate in various modes. Verify/Validate DFT requirements are being met pre-PD and Post-PD stages. Be a clear communicator with a proven ability to work across functions inside the company, and with partners across the globe. Requirements BSEE, MSEE, 10+ year experience in DFT techniques including JTAG, Scan, memory BIST, scan compression, ATPG vector generation, Mentor/Siemens Tessent Boundary Scan, and DFT for mixed-signal and digital Ips. Must have worked with 3rd party mixed-signal IP vendors in implementing DFT. Experience with timing constraint generation for DFT modes. Experience with LBIST – Initiation of test sequence on POST tests using IST controllers. Experience with IEEE JTAG 1149.1/1149.6/1500/1687 and BSDL, ICL, PDL. Experience with DFT verification and ATE test pattern generation. Experience with silicon bring-up and debugging on ATE and in-system