SOC Design Verification Engineer (San Jose)

Job Description : Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds. ○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. ○ Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.