DDR Engineer

Job Title:DDR EngineerLocation: Sanjose,CAKey skills: Zebu, FPGA , DDR (All generations) , ARM, DDR PHY, logic analyzers, oscilloscopes, and simulation waveformsEnsuring DDR PHY and controller designs adhere strictly to JEDEC standards (DDR4/DDR5/LPDDR5/LPDDR6)Using simulators (e.g., VCS) and emulators (e.g., ZeBu, Cadence Palladium) to debug design failures and root cause issues before tape-out.Validating power-sensitive LPDDR5 states, including self-refresh and deep power-down modes.Running simulations to verify timing margins, memory throughput, and latency, often collaborating on Python scripting for automation. Ensuring proper integration between the DDR controller, PHY, and SoC firmwareDevelop and execute test plans in C to validate the Features. In depth knowledge of one or more peripheral protocols and specifications Bare metal/Linux driver development, Firmware development.