Photonic Layout Design Engineer

Photonic Layout & Design Flow EngineerOn-site | Berkeley, CA | 5 days per weekUp to 220k base + equityI’m working with a well-funded photonic computing startup building optical processors for next-generation AI workloads.The company is developing an integrated platform spanning photonic and electronic ICs, packaging and system architecture. They are looking for a senior Photonic Layout & Design Flow Engineer to lead the complete PIC layout and tape-out workflow connecting the photonics and electronic design teams.This is not a component-only design position. You’ll own the path from individual photonic designs to a complete, verified and foundry-ready chip-level layout.You’ll work on problems such as:Leading commercial PIC layout and tape-outEstablishing and improving Cadence-based photonic design flowsIntegrating photonic components into complete chip-level layoutsWorking with photonic PDKs and foundry-process requirementsOwning DRC, LVS, sign-off and foundry submissionResolving PIC/EIC interfaces and shared design constraintsCoordinating photonics and electronic IC engineers toward tape-outIdentifying and closing layout, verification and integration risksLooking for engineers who have:Personally owned a commercial PIC layout and tape-out flowUsed Cadence Photonics, Cadence Virtuoso or a closely related commercial environmentExperience with PDKs, physical layout, verification and sign-offTaken photonic designs through foundry submissionWorked across PIC and EIC integrationBuilt or improved design workflows rather than relying entirely on established handoffsThe technical depth to guide other designers while remaining hands-onExperience with GlobalFoundries’ silicon-photonics technology is particularly relevant, although closely transferable commercial-foundry experience can also be considered. Python-based photonics tools can complement the profile but should not be the candidate’s only design environment.This is an opportunity to establish a foundational design capability and own a critical part of a new photonic computing platform.Worth a confidential chat?