Senior Design Verification Engineer

Job Description: We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.Key Responsibilities: Develop and maintain UVM-based verification environmentsCreate test plans, testcases, and coverage modelsPerform functional verification of RTL designsDebug RTL and testbench issuesDrive coverage closure (functional + code) Required Skills: Strong hands-on with SystemVerilog and UVMExperience in block-level verificationGood understanding of digital design fundamentalsExperience with debug tools (Verdi, DVE, etc.) Good to Have: Exposure to low-power verification (UPF)Experience with AMBA protocols (AXI/AHB/APB)