Lead Emulation Engineer

Leading the emulation strategy for next-generation AI inference ASICs, the full-time remote Lead Emulation Engineer will provide technical leadership, manage complex model builds, and collaborate across teams to ensure silicon readiness and accelerate firmware development. Key responsibilities Lead the partitioning and compilation of designs across a multi-rack Palladium environment for optimized performance and debugging Create and maintain hybrid emulation and co-simulation environments to enable software teams to run AI workloads on pre-silicon hardware Design and execute comprehensive emulation test plans to verify high-speed interfaces and complex AI memory hierarchies Required qualifications BS/MS in Electrical Engineering, Computer Engineering, or Computer Science 8+ years of experience in ASIC Emulation or Verification with a focus on large-scale Palladium installations Extensive hands-on experience with Cadence Palladium, including advanced clocking and In-Circuit Emulation Mastery of SystemVerilog, Verilog, and C/C++ for transactor development Deep understanding of data center protocols including PCIe, DDR, and AMBA AXI/NoC