FPGA Engineer with Security Clearance

Title: Senior FPGA Design EngineerLocation: Camden, NJ (100% On-Site)Type: 12 Months, Temp-to-Perm | Active Secret Clearance Required We are seeking a Senior FPGA Design Engineer to support a high-visibility defense program. The role involves FPGA architecture, design, development, and integration using VHDL and Xilinx Vivado toolchain. Responsibilities include algorithm mapping, verification, integration, revision control, and Earned Value Management (EVM) tracking.Requires 3–5+ years FPGA experience, Xilinx/Vivado expertise, revision control experience, and a STEM degree. Preferred skills include C++, Ethernet/TCP-IP/PCIe protocols, Xilinx SoC, PetaLinux, and HLS. Strong communication and collaboration skills are essential. Competitive pay and relocation benefits offered.