System Verification Engineer

Position: FPGA Verification Engineer Location: San Jose, CA - OnsiteJob Description & Responsibilities Own verification of entire FPGA design used in high-end router products Understand design specifications and interact with design engineers to identify verification scenarios Create test plans, constrained-random verification environments, test cases, regressions, and coverage reports Identify and write all types of coverage measures for stimulus and corner-cases Qualifications Strong academic background in Electrical Engineering (Bachelor’s required, Master’s preferred) pure verification experience in ASIC/FPGAs Proficient in SystemVerilog with clear OOP concepts Experience developing object-oriented testbench infrastructure, BFMs, and test cases in UVM Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO, etc. Understanding of verifying IP integrations, strategies, corner cases, etc. Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures Experience with scripting languages like Perl, Python is a plus Proficiency with industry-standard tools, revision control systems, and regression systems