Senior ASIC Design Flow Engineer - Cadence & Tapeouts

A leading technology company is seeking a Senior Applications and Solutions Engineer located in Santa Clara, California. The role involves providing critical technical support for advanced semiconductor processes and ensuring successful design implementations using Cadence tools. Candidates should have a strong background in advanced CMOS processes and significant experience in ASIC design. Competitive compensation and development opportunities in a hybrid work environment are offered. J-18808-Ljbffr