Principal DVE for AI Datacenter Chips (Hybrid)

A leading engineering recruitment firm is seeking a Top-Level Design Verification Engineer to join a well-funded startup in Mountain View, CA. This role involves owning verification processes for high-performance AI hardware, including defining methodologies, leading reviews, and developing infrastructure for testing. The ideal candidate will have extensive experience in verification, proficiency in SystemVerilog, and familiarity with high-performance compute systems. Join a dynamic team pushing the limits of GenAI technology in a hybrid work environment. #J-18808-Ljbffr