Physical Design Engineer

Overview In this role you contribute to the end-to-end physical design of cloud-grade silicon, from RTL to GDS, for macro and cluster levels under tight constraints. You’ll collaborate with cross-functional teams to optimize power, area, and performance while advancing design flows and signoff methodologies. The position sits within AWS UC’s semiconductor effort, focusing on cutting-edge architectures in a fast-paced environment. You’ll work on technologies powering the world’s largest cloud provider and shape next-generation devices. Compensation / Benefitsflexible work hoursmentorship and career growthinclusive culturediverse experiencesearth’s best employer initiative ResponsibilitiesEnd-to-end physical design of macros and clusters (RTL2GDS) under challenging constraintsDefine timing constraints and backend convergence aspectsDevelop and optimize design flows using EDA tools and vendors (Synopsys, Cadence)Plan and execute floorplanning, synthesis, clock tree, place-and-route, STA, PnR, and physical verificationPerform power and signal integrity analysis and equivalence checksDefine implementation and signoff methodologiesCollaborate with cross-functional teams to translate architecture into physical design solutions Key requirementsUnderstanding of the entire physical design flow (RTL to GDS)Deep understanding of sign-off activities (timing and physical verification)Experience with advanced node technologies and implementation toolsLeadership and mentoring abilitiesCollaboration across cross-functional teamsProblem-solving and creative thinkingFloorplanningSynthesisClock tree synthesis