Senior RTL/ASIC Design Lead for L1 Accelerator IP

A global telecom leader in Austin, TX, is looking for a Senior RTL Design Engineer to lead the microarchitecture of next-generation accelerators. This role involves transforming high-level architecture into high-performance hardware, taking ownership of major design blocks, and making critical design decisions. Ideal candidates will have extensive RTL design experience and expertise in SystemVerilog. This position offers a hybrid work environment with competitive compensation and benefits. #J-18808-Ljbffr