R&D Engineer

Overview In this role you will contribute to the design, simulation, prototyping and testing of wireless communication and sensing projects as part of the R&D Engineering team. You will build and maintain HDL testbenches, automate tests, and verify hardware, partnering with cross-functional colleagues to solve complex FPGA challenges. The position supports hybrid work with three on-site days and offers impact across full-system design, verification, and optimization. You will shape how high-performance FPGA systems meet product goals. ResponsibilitiesArchitect testbenches for full-system HDL simulationsMaintain and improve HDL testing infrastructureAutomate testing with scriptsCollect, maintain, and use code coverage data from test suitesDesign and code HDL blocksHardware verification and troubleshooting; familiarity with logic analyzers Key requirementsBachelor of Science in Electrical Engineering, Computer Science, or relevant field plus 4 years of FPGA design and testing/verification OR 2 years with MS in related fieldProven experience with multiple clock-domain, high-utilization FPGA designsExperience with Xilinx FPGAs, SoCs, and the Vivado IDEExperience with TCL or PythonFPGA design and testing/verificationHDL designTestbench developmentXilinx FPGAs and SoCsVivado IDETcl