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Strong working knowledge in the entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design, verification, synthesis, timing/STA, UPF, CLP, LEC formal verification, DFT, physical design.
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Drive improvements into static verification methodology PREFERRED EXPERIENCE: Exposure to power (UPF) / Clock domain crossing Having practices in formal verification Experience with emulation based power analysis Having RTL level power estimation experience is a plus x86 Architecture knowledge preferred Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Experienced with Verilog, System Verilog, Experience with C/C.
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A strong background in analog design and power electronics is a plus. 10+ Years working as a Design Verification Engineer in an Analog environment. This organization provides an opportunity to work on cutting edge products in Power and Power Management, Signal Chain, Standard Logic, etc.
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Candidate should have a strong background on power integrity analysis, timing analysis, automation, digital ASIC design flows, and circuit design. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
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Architect and develop the testbench using advanced verification methodology such as System Verilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
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As a member of Recogni’s ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications.
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Electrical Design Engineer REPORTS TO Engineering Manager Position Summary The Electrical design engineer will be responsible for designing digital and mixed-signal control and monitoring circuitry, PCB design and layout, and FPGA code development for state-of-the-art DC and AC power frequency converters.
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With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
$161,700 - $284,900 a yearExpandApply NowActive JobUpdated 9 days ago - UpvoteDownvoteShare Job
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Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification.
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We are seeking a Mid/Senior Process Piping Designer for Power Generation for our office in Overland Park, KS. This challenging position offers a competitive salary with exciting opportunities at a busy, employee-owned engineering firm.
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Preparing new generator interconnection applications, including development of conceptual single line diagram, verification of compliance with reactive power requirements, and development of PSS/E model to support the applications.
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RF amplifiers, impedance matching-networks, embedded processors, power electronics, FPGAs, A/Ds, DACs, op-amps, FETs, power supplies, working from prototype to full product release and applying creative test and verification methods that demonstrate requirements fulfillment (Microwave Office, SPICE, ADS, Altium, Allegro, etc.
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Experience with power system design experience consisting of circuit analysis and simulation, component selection, schematic capture, PCB design, and verification testing. Applied Physical Sciences (APS) is looking for a highly motivated power electronics engineer to join our Sensing and Communications Department.
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Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc. Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.
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This testing involves verification of CT/PT ratio, CT polarity, transformer impedance, power factor for transformers, timing of power circuit breakers, and insulation voltage withstand tests.
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