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In-depth technical expertise in one or more areas - DRAM memory array design, high-speed clocking and interface development, analog circuit design, digital/logic and custom circuit design, power delivery optimization, CMOS & semiconductor device physics, 2.5D and 3D packaging technologies.
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Familiarity with schematic entry and experience in digital (Verilog) and analog (FastSpice & Hspice) modeling and simulations. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only.
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Experience with circuit design in high speed circuits, Verilog/FPGAs, microcontrollers, microprocessors, firmware, and programmable logic based development. Experience with schematic and board design using Cadence OrCAD, Altium or equivalent.
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And firmware in Verilog or VHDL.Working knowledge of Xilinx design/debug tools and SoC (MPSoC or RFSoC) programmable logic devices. Development of interface middleware which facilitates access to FPGA programmable logic.
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Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging toolsKnowledge of logic design principles along with timing and power implicationsUnderstanding of low power microarchitecture techniquesUnderstanding of high-performance techniques and trade-offs in a CPU microarchitectureExperience in C or C.
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As a Sr. Digital Design Engineer in Micron's ASIC logic design team, you will be engaged in the design of the next generation of Micron's internally developed ASICs and controller IP. The ideal candidate will be a driven individual looking to advance into the high-speed ASIC and memory controller design industry.
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Confirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering outstanding PHY designs.
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Experienced with memory simulator such as HSPICE, HSIM, Verilog, and layout tool and verification software required. Perform chip architecture, logic/circuit design, and simulation and optimization ISSI products.
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Designing and implementing video compression logic, image processing logic, and computer vision processors in Verilog and SystemVerilog. Very Good understanding of Computer architecture, Microprocessor, Digital electronics, VLSI/ASIC design, and Logic design.
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Verilog, System Verilog, and scripting. In-depth knowledge of digital logic design, CPU architecture and microarchitecture. Submit Resume CPU Processor Performance Verification Engineer.
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3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance, and power, as well as low-power design techniques.
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Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python. Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.
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As a Principal Digital Design Engineer in Micron's ASIC logic design team, you will develop and lead the design of the next generation of Micron's internally developed ASICs and controller IP. The ideal candidate will be a driven individual looking to advance into the high-speed ASIC and memory controller design industry.
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5 years in ASIC/SOC design and Verilog RTL coding experience. The candidate will be a part of the I/O design team responsible for specifying, implementing and integrating Verilog RTL IPs into our custom high performance, energy efficient AI processor.
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As a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to generating block level static timing constraints.
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