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Verification Engineer
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- Verify complex design blocks using equally complex SV/UVM verification environments
- Strong background in SystemVerilog and UVM verification methodologies
- PHY verification experience, including some amount of mixed signal verification experience is desirable
- Summary Over 9 years’ experience in ASIC verification, with several successful and functional devices
- Experience in FPGA design (RTL) and verification (Altera and Xilinx)
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