Upvote
Downvote
Senior Staff Engineer, Verification (Ethernet, Serdes, UVM)
Share Job
- Suggest Revision
Full-time
- Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
- IP/SOC/ASIC DV engineer responsible for planning and coordinating the design verification, and evaluation in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality.
- Lead the development and execution of IP/SOC/ASIC DV plans
- Understand IP/SOC/ASIC verification flows and methodologies
- Strong verification knowledge and hands on experience with SystemVerilog and UVM
Active Job
Updated YesterdaySimilar Job
Relevance
Active