Broadcom

The ideal candidate will have expertise in integrated-circuit process technologies, and semiconductor assembly including manufacturability and reliability issues with wide-ranging experience in semiconductor device fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure mechanisms and testing, assembly process development and qualification, design kit development and wafer foundry manufacturing operations.. Knowledge and use of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design. Experience with usage of device model usage, layout and circuit simulation tools, Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification. Provide design support for IP & ASIC to create robust designs in line with advanced semiconductor and packaging process flows & constraints. Bachelor’s degree in electrical engineering and 8+ years (OR) Master’s degree and 6+ years (OR) PhD and 3+ years of experience in semiconductor process technology and manufacturing, specifically R&D and integration roles

engineer

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Job Description:
R&D Staff Engineer
The ideal candidate will have expertise in integrated-circuit process technologies, and semiconductor assembly including manufacturability and reliability issues with wide-ranging experience in semiconductor device fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure mechanisms and testing, assembly process development and qualification, design kit development and wafer foundry manufacturing operations. Serves as an internal investigator for new technology projects and is capable of independent project management from concept phase through transfer to high-volume manufacturing, facilitating clear communication with external foundry & assembly collaborators as well as internal design and validation teams throughout the project. Can perform risk assessment and help to coordinate cross-functional technology risk mitigation for multiple projects in parallel. Typically possesses a graduate degree in electrical engineering and has several years of experience in the field.
Key Qualifications
Broad knowledge of advanced silicon and packaging process technologies
Working knowledge of the Advanced Semiconductor Technology nodes including FinFET and Gate All Around technology; Design experience is a plus
Working knowledge of 2.5D packaging technology and 3D stacked IC
Knowledge and use of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design
Working knowledge of IP and chip design flow for analog and digital
Experience with parametric and yield data analysis. Proficiency with statistical data analysis tools
Experience with usage of device model usage, layout and circuit simulation tools, Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification
Conducting design reviews & creating slides and other associated documentation
Assisting with integration of IP into SOCs and creating guidelines
Experience with yield failure mechanisms and tools for root cause finding (EFA, PFA); Familiarity with device reliability degradation mechanisms, test methods, and lifetime modeling
Exceptional data analysis, problem solving, and interpersonal skills
Being able to work with large teams from manufacturing, technology and packaging
Job Description
Provide design support for IP & ASIC to create robust designs in line with advanced semiconductor and packaging process flows & constraints
Work closely with technology experts and Silicon manufacturing teams to deploy the technology requirements for ASIC product design & design automation flows
Define process flows, design rules and IP adaptation guidelines for the advanced semiconductor technology and advanced packaging technology
Define technology test vehicles for advanced technology & packaging for validation before product manufacturing
Provide design rule reviews for IP, chip, and package designs for product release sign off
Provide support for timing, physical verification signoff to make IP & ASIC designs robust
Perform WAT & yield analysis on testchips and products to evaluate IP margins & robustness
Work with IP design teams to support adaptation of existing IP into various semiconductor packaging environments
Assist with technology road mapping activity for selection of appropriate semiconductor and packaging technology for ASICs to meet end customer requirements
Education & Experience
Bachelor’s degree in electrical engineering and 8+ years (OR) Master’s degree and 6+ years (OR) PhD and 3+ years of experience in semiconductor process technology and manufacturing, specifically R&D and integration roles
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $91,200 - $178,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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