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Physical Design Engineer Engineering - Electrical (Semiconductor) Mountain View, California
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- The right candidate is an experienced physical design engineer who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, initial floor plan exploration (in conjunction with microarchitecture definition), through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout.
- Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and the interconnect topologies.
- Establish the P+R workflow at the block and chip levels, working with large and complex designs in the latest process technology nodes, at leading edge scale and performance.
- Execute on block-level and top-level physical implementation, from floorplan and power plan, through P+R, through timing closure, LVS/DRC/ERC/ANT checks, and tapeout.
- Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff.
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