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Lead Digital Design Verification Engineer - UVM
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- Job Title: ASIC/FPGA Verification Engineer - UVM
- The Client is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs∯*∯
- In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation, and communications.
- Fluent in System Verilog including SVA.
- Recent experience with UVM
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