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FPGA Engineer R & D
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$164,000 a year
Full-time
- Seeking motivated entry to senior level FPGA engineers to join our growing Communication and Signal Processing (CSP) Division at the Applied Research Laboratory (ARL) at Penn State University.
- Design real-time digital signal processing systems using FPGAs
- Experience with VHDL and/or Verilog
- Knowledge and exposure to prototyping, signal processing, FPGA, cellular, wireless, algorithms, communications and creative thinking
- Being situated in central Pennsylvania, we are situated near 4 state parks, have miles of biking and hiking trails and many streams and lakes for fishing and water sports.
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