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Digital Design Engineer
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$150,000 - $200,000 a year
Full-time
- Develop complex SOC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
- RTL design of modules through System Verilog HDL coding, adhering to quality standards.
- SOC level configuration and integration of digital and mixed-signal IPs. Examples include embedded processors, memory and controllers, busses, power and clocking systems, security systems, machine learning, radio systems, analog IP, and pads.
- Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production
- Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools
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