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Design Verification Engineer
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- Job description: Our client develops and delivers ASIC and SoC solutions to customers worldwide in some of the hottest technology areas.
- If you are a hands-on DV Engineer with strong UVM skills and can be client facing, wed like to speak with you.
- Responsible for verification of ASIC designs including: Design Verification Implement test benches in UVM and System Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
- Setup Verification Regression suites at RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case conditions.
- Must have strong experience with UVM. Can do UVM from scratch.
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