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Design Verification Engineer
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- DescriptionWe are looking for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office.
- Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
- You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
- Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
- Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
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