Veracity Software Inc

Analog IC Design Engineer, Senior Staff (T4). The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.. Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques. Modeling of passive on-chip elements such as inductor, T-coil, and transformer

analog ic design engineer

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Analog IC Design Engineer, Senior Staff (T4)

Hybrid

2 days a week in the office

Santa Clara, CA

You will be working with multi-functional teams to deliver high-speed Ethernet products. You will define specifications based on link budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally, with the team, you will drive designs into volume production and delight customers.

What We're Looking For

Master's degree and/or PhD in Electrical Engineering and 3+ years of experience.

 * The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.

 * Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters 
 * In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques 
 * Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization

EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:

 * Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE 
 * Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) 
 * Familiarity with CDR architectures and implementations 
 * Design experience in advanced CMOS technologies, design with FinFet technology

 * Experience in lab testing of high-speed transceivers 
 * Modeling of passive on-chip elements such as inductor, T-coil, and transformer 
 * Able to build VerilogA/AMS behavioral models 
 * Able to analyze and lead characterization data from lab and volume testing 
 * Knowledge of ESD requirements
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