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Digital Design Engineer
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- FPGA design experience using Verilog, SystemVerilog, AMD/Xilinx FPGA design (Kintex/Virtex UltraScale+ desired, 7-series minimum)
- Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
- Contribute to ASIC digital architecture, design and verification
- 5+ years of FPGA design experience using Verilog, SystemVerilog
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