{"schemaVersion":"jobsearcher.job.v1","id":"f8cfd10bc430bb8748f6c66c","url":"https://jobsearcher.com/jobs/f8cfd10bc430bb8748f6c66c","canonicalUrl":"https://jobsearcher.com/jobs/f8cfd10bc430bb8748f6c66c","title":"Silicon Debug Engineer","description":"Santa Clara, California, United States Hardware\n\nDo you have a passion for solving the hardest problems in silicon? Do you thrive at the intersection of circuit theory, device physics, and hands‑on failure investigation? As part of our Silicon Debug group, you'll take complex, often elusive silicon failures and systematically uncover their root cause — from electrical characterization all the way down to physical analysis. You and your team will apply deep engineering fundamentals and cutting‑edge failure analysis techniques to enable product ramp at scale. Your efforts will directly impact the quality and reliability of state‑of‑the‑art ASICs that power experiences for millions of customers worldwide. Join us, and you'll play a central role in ensuring the silicon we build is everything it needs to be.\n\nDescription\nImagine yourself at the center of our SoC bring‑up and product ramp effort, collaborating across circuit design, process engineering, DFT, and failure analysis teams — with a critical impact on getting functional products to millions of customers quickly.\n\nResponsibilities\n\nDrive the silicon debug effort involving custom circuits from initial bring‑up through volume ramp, owning failure isolation from symptom to root cause.\n\nWork with circuit design teams to define silicon characterization and debug requirements for test chips and product chips.\n\nEngage with PE / DFT / FA teams to plan and execute electrical and physical characterization strategies.\n\nPerform design analysis, modeling/simulation, SPICE simulation, statistical analysis, and silicon bring‑up to understand and reproduce failure signatures.\n\nWork closely with systems and lab teams to reproduce circuit‑level behavior using MBIST, functional diagnostics, and characterization structures.\n\nPlan and interpret FA analysis — translating electrical failure signatures into targeted physical analysis strategies and understanding how FA technique choices impact observable circuit behavior.\n\nLeverage eFA and pFA techniques including Dynamic Laser Stimulus (DLS), Lock‑in Thermography (LIT), Nanoprobe, Focused Ion Beam (FIB), TEM/SEM, EMMI, and Physical Failure Analysis (PFA) to identify defect mechanisms and localize failures to specific circuit nodes.\n\nUnderstand the circuit impact of FA techniques — including how photon emission, voltage contrast, charge injection, sample preparation, and probe‑induced perturbations may influence or mask failure modes during analysis.\n\nMinimum Qualifications\n\nBSEE/MSEE\n\nPreferred Qualifications\n\nExperience in one or more of the following areas: SRAM circuits, custom circuit design, silicon debug.\n\nExperience in design or debug of low‑voltage / low‑power custom circuits.\n\nDeep understanding of deep‑submicron device physics, leakage mechanisms, and technology interactions with device behavior.\n\nSolid understanding of device matching, device noise sources (1/f, thermal), extrinsic noise sources (supply noise, jitter), and their impact on high‑precision circuits.\n\nFamiliarity with electrical failure analysis (eFA) techniques and physical failure analysis (pFA) workflows, and the ability to plan FA strategies based on electrical debug data.\n\nUnderstanding of Dynamic Lock‑in Thermography (DLS) and Lock‑in Thermography (LIT) for localization of resistive and leakage defects, including their sensitivity limits and how thermal signatures correlate to specific circuit fault modes.\n\nKnowledge of Nanoprobe techniques for electrical probing of deep‑submicron nodes, and appreciation of how probe contact, voltage bias, and electron beam exposure can perturb sensitive analog or memory circuits.\n\nAwareness of how physical sample preparation steps (deprocessing, FIB cross‑section, delayering) can alter or destroy evidence of electrical failures, and how to coordinate FA plans that preserve failure signatures.\n\nAbility to interpret FA results (photon emission maps, OBIRCH, thermal maps, TEM/SEM imagery) in the context of circuit topology and failure electrical signatures.\n\nAbility to conduct structured experiments during silicon debug, gather and analyze large datasets, and utilize scripting to support efficient handling of debug data.\n\nProficiency in scripting languages (Python, Perl, or others) and CAD automation tools.\n\nKnowledge of industry‑standard circuit design and simulation tools.\n\nAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location.\n\nApple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.\n\nNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.\n\nApple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics.\n\nAt Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.\n\n#J-18808-Ljbffr","company":"Apple","rawCompany":"apple","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-30T03:58:18.741Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Silicon Debug Engineer","description":"Santa Clara, California, United States Hardware\n\nDo you have a passion for solving the hardest problems in silicon? Do you thrive at the intersection of circuit theory, device physics, and hands‑on failure investigation? As part of our Silicon Debug group, you'll take complex, often elusive silicon failures and systematically uncover their root cause — from electrical characterization all the way down to physical analysis. You and your team will apply deep engineering fundamentals and cutting‑edge failure analysis techniques to enable product ramp at scale. Your efforts will directly impact the quality and reliability of state‑of‑the‑art ASICs that power experiences for millions of customers worldwide. Join us, and you'll play a central role in ensuring the silicon we build is everything it needs to be.\n\nDescription\nImagine yourself at the center of our SoC bring‑up and product ramp effort, collaborating across circuit design, process engineering, DFT, and failure analysis teams — with a critical impact on getting functional products to millions of customers quickly.\n\nResponsibilities\n\nDrive the silicon debug effort involving custom circuits from initial bring‑up through volume ramp, owning failure isolation from symptom to root cause.\n\nWork with circuit design teams to define silicon characterization and debug requirements for test chips and product chips.\n\nEngage with PE / DFT / FA teams to plan and execute electrical and physical characterization strategies.\n\nPerform design analysis, modeling/simulation, SPICE simulation, statistical analysis, and silicon bring‑up to understand and reproduce failure signatures.\n\nWork closely with systems and lab teams to reproduce circuit‑level behavior using MBIST, functional diagnostics, and characterization structures.\n\nPlan and interpret FA analysis — translating electrical failure signatures into targeted physical analysis strategies and understanding how FA technique choices impact observable circuit behavior.\n\nLeverage eFA and pFA techniques including Dynamic Laser Stimulus (DLS), Lock‑in Thermography (LIT), Nanoprobe, Focused Ion Beam (FIB), TEM/SEM, EMMI, and Physical Failure Analysis (PFA) to identify defect mechanisms and localize failures to specific circuit nodes.\n\nUnderstand the circuit impact of FA techniques — including how photon emission, voltage contrast, charge injection, sample preparation, and probe‑induced perturbations may influence or mask failure modes during analysis.\n\nMinimum Qualifications\n\nBSEE/MSEE\n\nPreferred Qualifications\n\nExperience in one or more of the following areas: SRAM circuits, custom circuit design, silicon debug.\n\nExperience in design or debug of low‑voltage / low‑power custom circuits.\n\nDeep understanding of deep‑submicron device physics, leakage mechanisms, and technology interactions with device behavior.\n\nSolid understanding of device matching, device noise sources (1/f, thermal), extrinsic noise sources (supply noise, jitter), and their impact on high‑precision circuits.\n\nFamiliarity with electrical failure analysis (eFA) techniques and physical failure analysis (pFA) workflows, and the ability to plan FA strategies based on electrical debug data.\n\nUnderstanding of Dynamic Lock‑in Thermography (DLS) and Lock‑in Thermography (LIT) for localization of resistive and leakage defects, including their sensitivity limits and how thermal signatures correlate to specific circuit fault modes.\n\nKnowledge of Nanoprobe techniques for electrical probing of deep‑submicron nodes, and appreciation of how probe contact, voltage bias, and electron beam exposure can perturb sensitive analog or memory circuits.\n\nAwareness of how physical sample preparation steps (deprocessing, FIB cross‑section, delayering) can alter or destroy evidence of electrical failures, and how to coordinate FA plans that preserve failure signatures.\n\nAbility to interpret FA results (photon emission maps, OBIRCH, thermal maps, TEM/SEM imagery) in the context of circuit topology and failure electrical signatures.\n\nAbility to conduct structured experiments during silicon debug, gather and analyze large datasets, and utilize scripting to support efficient handling of debug data.\n\nProficiency in scripting languages (Python, Perl, or others) and CAD automation tools.\n\nKnowledge of industry‑standard circuit design and simulation tools.\n\nAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location.\n\nApple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.\n\nNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.\n\nApple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics.\n\nAt Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.\n\n#J-18808-Ljbffr","datePosted":"2026-06-30T03:58:18.741Z","dateModified":"2026-06-30T03:58:18.741Z","hiringOrganization":{"@type":"Organization","name":"Apple","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"f8cfd10bc430bb8748f6c66c"},"url":"https://jobsearcher.com/jobs/f8cfd10bc430bb8748f6c66c"}}