{"schemaVersion":"jobsearcher.job.v1","id":"f8a34d9b62b80b1983f0e738","url":"https://jobsearcher.com/jobs/f8a34d9b62b80b1983f0e738","canonicalUrl":"https://jobsearcher.com/jobs/f8a34d9b62b80b1983f0e738","title":"PCIe Silicon Validation & Debug Engineer","description":"Job Description:\nSummary\nWe are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deep expertise in PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, and debug across both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance of PCIe IP and SoC-level interconnects.\nKey Responsibilities\nPre-Silicon\nDevelop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration\nCreate directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality\nPerform protocol-level analysis using VIP (Verification IP) environments and bus functional models\nDebug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling\nCollaborate with design teams on coverage closure, assertions, and functional coverage models\nPost-Silicon\nBring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)\nDevelop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance\nDebug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers\nPerform root-cause analysis of PCIe link failures, packet errors, and performance degradation\nCharacterize PCIe PHY performance including jitter, eye diagrams, and signal integrity\nCollaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues\nDrive compliance and interoperability testing per PCI-SIG specifications\nGeneral\nAnalyze PCIe specification updates and assess impact on existing IP/SOC designs\nAutomate test infrastructure, result parsing, and regression frameworks\nDocument findings, debug methodologies, and test coverage metrics\nContribute to team knowledge sharing\nRequired Qualifications\nEducation: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\nExperience: 3–8+ years of experience in PCIe validation, verification, or silicon bring-up\nStrong understanding of PCIe specification (Gen3 through Gen5/Gen6), including:\nTransaction Layer: TLP types, ordering rules, flow control, completion handling\nData Link Layer: ACK/NAK, replay, LCRC, DLLP\nPhysical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)\nPower management: ASPM, L-states, D-states\nProficiency in System Verilog/UVM for pre-silicon test development\nExperience with protocol analyzers and lab debug tools for post-silicon validation\nFamiliarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing\nSolid understanding of PCIe enumeration, BAR programming, and configuration space\nExperience with FPGA prototyping or emulation platforms is a plus\nPreferred Qualifications\nExperience with CXL (Compute Express Link) or other PCIe-based protocols\nKnowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)\nFamiliarity with compliance testing per PCI-SIG specifications and test suites\nExperience with NVMe, CCIX, or UCIe protocols\nBackground in SoC-level integration and system-level validation\nUnderstanding of BIOS/firmware interactions with PCIe subsystems\nContributions to PCIe IP development or architecture definition\nPay: From $70.00 per hour\nWork Location: In person","company":"Excelon Solutions","rawCompany":"excelon solutions","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-07T10:59:22.372Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"PCIe Silicon Validation & Debug Engineer","description":"Job Description:\nSummary\nWe are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deep expertise in PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, and debug across both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance of PCIe IP and SoC-level interconnects.\nKey Responsibilities\nPre-Silicon\nDevelop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration\nCreate directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality\nPerform protocol-level analysis using VIP (Verification IP) environments and bus functional models\nDebug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling\nCollaborate with design teams on coverage closure, assertions, and functional coverage models\nPost-Silicon\nBring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)\nDevelop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance\nDebug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers\nPerform root-cause analysis of PCIe link failures, packet errors, and performance degradation\nCharacterize PCIe PHY performance including jitter, eye diagrams, and signal integrity\nCollaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues\nDrive compliance and interoperability testing per PCI-SIG specifications\nGeneral\nAnalyze PCIe specification updates and assess impact on existing IP/SOC designs\nAutomate test infrastructure, result parsing, and regression frameworks\nDocument findings, debug methodologies, and test coverage metrics\nContribute to team knowledge sharing\nRequired Qualifications\nEducation: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\nExperience: 3–8+ years of experience in PCIe validation, verification, or silicon bring-up\nStrong understanding of PCIe specification (Gen3 through Gen5/Gen6), including:\nTransaction Layer: TLP types, ordering rules, flow control, completion handling\nData Link Layer: ACK/NAK, replay, LCRC, DLLP\nPhysical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)\nPower management: ASPM, L-states, D-states\nProficiency in System Verilog/UVM for pre-silicon test development\nExperience with protocol analyzers and lab debug tools for post-silicon validation\nFamiliarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing\nSolid understanding of PCIe enumeration, BAR programming, and configuration space\nExperience with FPGA prototyping or emulation platforms is a plus\nPreferred Qualifications\nExperience with CXL (Compute Express Link) or other PCIe-based protocols\nKnowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)\nFamiliarity with compliance testing per PCI-SIG specifications and test suites\nExperience with NVMe, CCIX, or UCIe protocols\nBackground in SoC-level integration and system-level validation\nUnderstanding of BIOS/firmware interactions with PCIe subsystems\nContributions to PCIe IP development or architecture definition\nPay: From $70.00 per hour\nWork Location: In person","datePosted":"2026-08-07T10:59:22.372Z","dateModified":"2026-08-07T10:59:22.372Z","hiringOrganization":{"@type":"Organization","name":"Excelon Solutions","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"f8a34d9b62b80b1983f0e738"},"url":"https://jobsearcher.com/jobs/f8a34d9b62b80b1983f0e738"}}