{"schemaVersion":"jobsearcher.job.v1","id":"f4e96f01002c8e67e8f00bd8","url":"https://jobsearcher.com/jobs/f4e96f01002c8e67e8f00bd8","canonicalUrl":"https://jobsearcher.com/jobs/f4e96f01002c8e67e8f00bd8","title":"DFT Intern (12 Week Internship)","description":"Requirements\n\nYou do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment\n\nProgress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field\n\nFamiliarity with a hardware description language (Verilog or SystemVerilog)\n\nExposure to ASIC or SoC design concepts\n\nFamiliarity with digital logic design fundamentals\n\nFamiliarity with standard ASIC design flow steps (synthesis, STA, DFT)\n\nFamiliarity with scripting in Python, Tcl, or another language\n\nAre able to learn quickly about transformers and other aspects of modern artificial intelligence\n\n(Desirable) Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression\n\n(Desirable) Experience with Tessent or similar DFT tooling\n\n(Desirable) Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)\n\n(Desirable) Exposure to DFT flow automation or regression infrastructure\n\n(Desirable) Familiarity with clocking and reset schemes\n\nWe encourage you to apply even if you do not believe you meet every single qualification\n\nWhat the job involves\n\nAs a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius\n\nYou will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models\n\nWe do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed\n\nWe are looking for Summer ’26, Fall ’26, Spring ’27, and Summer ’27 interns\n\n12‑week paid internship\n\n#J-18808-Ljbffr","company":"Etched","rawCompany":"etched","city":"Millbrae","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-20T04:10:52.626Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-3023.00","title":"Electrical and Electronic Engineering Technologists and Technicians","slug":"electrical-and-electronic-engineering-technologists-and-technicians"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"DFT Intern (12 Week Internship)","description":"Requirements\n\nYou do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment\n\nProgress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field\n\nFamiliarity with a hardware description language (Verilog or SystemVerilog)\n\nExposure to ASIC or SoC design concepts\n\nFamiliarity with digital logic design fundamentals\n\nFamiliarity with standard ASIC design flow steps (synthesis, STA, DFT)\n\nFamiliarity with scripting in Python, Tcl, or another language\n\nAre able to learn quickly about transformers and other aspects of modern artificial intelligence\n\n(Desirable) Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression\n\n(Desirable) Experience with Tessent or similar DFT tooling\n\n(Desirable) Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)\n\n(Desirable) Exposure to DFT flow automation or regression infrastructure\n\n(Desirable) Familiarity with clocking and reset schemes\n\nWe encourage you to apply even if you do not believe you meet every single qualification\n\nWhat the job involves\n\nAs a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius\n\nYou will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models\n\nWe do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed\n\nWe are looking for Summer ’26, Fall ’26, Spring ’27, and Summer ’27 interns\n\n12‑week paid internship\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T04:10:52.626Z","dateModified":"2026-06-20T04:10:52.626Z","hiringOrganization":{"@type":"Organization","name":"Etched","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Millbrae","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"f4e96f01002c8e67e8f00bd8"},"url":"https://jobsearcher.com/jobs/f4e96f01002c8e67e8f00bd8"}}