{"schemaVersion":"jobsearcher.job.v1","id":"f2df4ee4a2bb2c21e469b04a","url":"https://jobsearcher.com/jobs/f2df4ee4a2bb2c21e469b04a","canonicalUrl":"https://jobsearcher.com/jobs/f2df4ee4a2bb2c21e469b04a","title":"Principal Engineer - CAD (Physical Verification)","description":"Overview\nIn this role you will support and develop physical verification flows for multiple process nodes at Microchip. You will collaborate with Layout, Design, and Technology Development to ensure reliable, manufacturable silicon through advanced EDA tools. You’ll build regression tests, automate verification flows, and debug PV issues, impacting device quality and yield. This is a hands-on role in a global CAD team that enables innovation across a broad technology portfolio.\n\nResponsibilitiesDevelop physical verification regression tests for QA of PV decksSupport Layout and Design engineers with PV activities using Calibre, Pegasus, or Synopsys HerculesCreate and maintain verification run decks and automate flowsContribute to ESD, ERC, Voltage-Aware DRC, via doubling methodologiesDevelop and enhance DRC rules and design-for-manufacturability checks with Technology DevelopmentBuild and verify foundry rule decks and support remote sitesDebug and resolve PV issues and improve flow quality and reliabilityWork in a team to extend flows across multiple PDKs and process nodes\nKey requirementsBachelor in Electrical Engineering or related field with 10 years in physical verificationDeep knowledge of Calibre DesignRev scriptingFluent with SVRF and TVFProficient at debugging PV issues with RVE, Vue, or other EDA visualizersExperience customizing Calibre InteractiveStrong Tcl/Tk, Perl, Python programmingSolid understanding of layout rules, device identification, and foundry rulesKnowledge of Design for Manufacturing affecting quality, reliability, and yieldExperience with Cadence Virtuoso and/or CalibreDRVExcellent verbal and written communication skillsexcellent communicationinterpersonal skillsteam collaborationSiemens CalibreCadence PegasusSynopsys Hercules","company":"Microchip Technology","rawCompany":"microchip technology","city":"Phoenix","state":"AZ","isRemote":false,"isActive":false,"createdAt":"2026-09-15T03:45:36.789Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Principal Engineer - CAD (Physical Verification)","description":"Overview\nIn this role you will support and develop physical verification flows for multiple process nodes at Microchip. You will collaborate with Layout, Design, and Technology Development to ensure reliable, manufacturable silicon through advanced EDA tools. You’ll build regression tests, automate verification flows, and debug PV issues, impacting device quality and yield. This is a hands-on role in a global CAD team that enables innovation across a broad technology portfolio.\n\nResponsibilitiesDevelop physical verification regression tests for QA of PV decksSupport Layout and Design engineers with PV activities using Calibre, Pegasus, or Synopsys HerculesCreate and maintain verification run decks and automate flowsContribute to ESD, ERC, Voltage-Aware DRC, via doubling methodologiesDevelop and enhance DRC rules and design-for-manufacturability checks with Technology DevelopmentBuild and verify foundry rule decks and support remote sitesDebug and resolve PV issues and improve flow quality and reliabilityWork in a team to extend flows across multiple PDKs and process nodes\nKey requirementsBachelor in Electrical Engineering or related field with 10 years in physical verificationDeep knowledge of Calibre DesignRev scriptingFluent with SVRF and TVFProficient at debugging PV issues with RVE, Vue, or other EDA visualizersExperience customizing Calibre InteractiveStrong Tcl/Tk, Perl, Python programmingSolid understanding of layout rules, device identification, and foundry rulesKnowledge of Design for Manufacturing affecting quality, reliability, and yieldExperience with Cadence Virtuoso and/or CalibreDRVExcellent verbal and written communication skillsexcellent communicationinterpersonal skillsteam collaborationSiemens CalibreCadence PegasusSynopsys Hercules","datePosted":"2026-09-15T03:45:36.789Z","dateModified":"2026-09-15T03:45:36.789Z","hiringOrganization":{"@type":"Organization","name":"Microchip Technology","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Phoenix","addressRegion":"AZ","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"f2df4ee4a2bb2c21e469b04a"},"url":"https://jobsearcher.com/jobs/f2df4ee4a2bb2c21e469b04a"}}