{"schemaVersion":"jobsearcher.job.v1","id":"efde97b993dc48d449e6af4e","url":"https://jobsearcher.com/jobs/efde97b993dc48d449e6af4e","canonicalUrl":"https://jobsearcher.com/jobs/efde97b993dc48d449e6af4e","title":"Lead ASIC Design Engineer","description":"Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.\r\nOur Values\r\nBe Fearless: Unmute yourself. Test boundaries and get proven right.\r\nRemain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.\r\nEducate Your Ego: Selflessly collaborate towards our shared purpose.\r\nAbout the Role\r\nWe're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership , guiding teams from architecture through tapeout.\r\nThe ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments.\r\nWhat You'll Do\r\nOwn end-to-end RTL design for major subsystems or full-chip blocks.\r\nDefine micro-architecture aligned with PPA (Power, Performance, Area) targets.\r\nLead and mentor a team of RTL engineers (junior to senior ICs).\r\nDrive design reviews , coding standards, and best practices.\r\nCollaborate closely with\r\nDesign Verification (DV)\r\nPhysical Design (PD)\r\nSTA / Timing / DFT teams\r\nEnsure high RTL quality via\r\nLint, CDC, RDC checks\r\nLow-power (UPF) compliance\r\nDebug complex issues across\r\nRTL simulation\r\nGate-Level Simulation (GLS)\r\nSilicon bring-up\r\nWork with foundry and backend constraints (timing, congestion, IR, etc.).\r\nDrive schedule, risk mitigation, and execution toward tapeout.\r\nRequired Qualifications\r\nBachelor's or Master's in Electrical / Computer Engineering.\r\n10+ years of experience in ASIC/SoC RTL design.\r\nExpert-level proficiency in:\r\nSystemVerilog / Verilog RTL coding\r\nMicro-architecture design\r\nStrong understanding of\r\nTiming (setup/hold, STA correlation)\r\nCDC/RDC methodologies\r\nReset strategies and clocking architectures\r\nLow-power design (UPF/CPF)\r\nProven experience leading blocks through multiple tapeouts .\r\nHands-on experience with synthesis (e.g., Design Compiler).\r\nStrong debugging and problem-solving ability.\r\nExcellent communication across cross-functional teams.\r\nOwnership and accountability for silicon success.\r\nAbility to operate under tight tapeout schedules.\r\nPreferred Qualifications\r\nExperience in advanced nodes (e.g., 12FFC, 7nm, 5nm).\r\nStrong GLS expertise (SDF, X-propagation, power-aware sims).\r\nKnowledge of DFT (scan, MBIST, compression).\r\nExperience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems.\r\nScripting proficiency (Python / Tcl).\r\nPrior collaboration with foundries such as TSMC.\r\nExperience in startup environments or first-silicon efforts.\r\nExposure to packaging (flip-chip, bump planning, IO constraints).\r\nExperience with low-frequency testchips or rapid prototyping.\r\nGovernment clearance is preferred.\r\nLeadership Expectations\r\nProvide technical direction and architectural clarity .\r\nMentor and grow team members.\r\nDrive high engineering standards and design quality.\r\nInfluence cross-functional decisions.\r\nBalance hands-on work with leadership responsibilities.\r\nCompensation Range\r\n$220,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.\r\nBenefits\r\nMedical, Dental, & Vision – 100% covered premiums.\r\nEquity – Stock Options.\r\n401(k) match.\r\nWFH Hardware.\r\nBolt is committed to building a diverse and inclusive environment in which we recognize and value each other's differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.\r\nJ-18808-Ljbffr","company":"Bolt Graphics","rawCompany":"bolt graphics","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-08T01:59:22.243Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"11-9041.00","title":"Architectural and Engineering Managers","slug":"architectural-and-engineering-managers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Lead ASIC Design Engineer","description":"Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.\r\nOur Values\r\nBe Fearless: Unmute yourself. Test boundaries and get proven right.\r\nRemain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.\r\nEducate Your Ego: Selflessly collaborate towards our shared purpose.\r\nAbout the Role\r\nWe're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership , guiding teams from architecture through tapeout.\r\nThe ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments.\r\nWhat You'll Do\r\nOwn end-to-end RTL design for major subsystems or full-chip blocks.\r\nDefine micro-architecture aligned with PPA (Power, Performance, Area) targets.\r\nLead and mentor a team of RTL engineers (junior to senior ICs).\r\nDrive design reviews , coding standards, and best practices.\r\nCollaborate closely with\r\nDesign Verification (DV)\r\nPhysical Design (PD)\r\nSTA / Timing / DFT teams\r\nEnsure high RTL quality via\r\nLint, CDC, RDC checks\r\nLow-power (UPF) compliance\r\nDebug complex issues across\r\nRTL simulation\r\nGate-Level Simulation (GLS)\r\nSilicon bring-up\r\nWork with foundry and backend constraints (timing, congestion, IR, etc.).\r\nDrive schedule, risk mitigation, and execution toward tapeout.\r\nRequired Qualifications\r\nBachelor's or Master's in Electrical / Computer Engineering.\r\n10+ years of experience in ASIC/SoC RTL design.\r\nExpert-level proficiency in:\r\nSystemVerilog / Verilog RTL coding\r\nMicro-architecture design\r\nStrong understanding of\r\nTiming (setup/hold, STA correlation)\r\nCDC/RDC methodologies\r\nReset strategies and clocking architectures\r\nLow-power design (UPF/CPF)\r\nProven experience leading blocks through multiple tapeouts .\r\nHands-on experience with synthesis (e.g., Design Compiler).\r\nStrong debugging and problem-solving ability.\r\nExcellent communication across cross-functional teams.\r\nOwnership and accountability for silicon success.\r\nAbility to operate under tight tapeout schedules.\r\nPreferred Qualifications\r\nExperience in advanced nodes (e.g., 12FFC, 7nm, 5nm).\r\nStrong GLS expertise (SDF, X-propagation, power-aware sims).\r\nKnowledge of DFT (scan, MBIST, compression).\r\nExperience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems.\r\nScripting proficiency (Python / Tcl).\r\nPrior collaboration with foundries such as TSMC.\r\nExperience in startup environments or first-silicon efforts.\r\nExposure to packaging (flip-chip, bump planning, IO constraints).\r\nExperience with low-frequency testchips or rapid prototyping.\r\nGovernment clearance is preferred.\r\nLeadership Expectations\r\nProvide technical direction and architectural clarity .\r\nMentor and grow team members.\r\nDrive high engineering standards and design quality.\r\nInfluence cross-functional decisions.\r\nBalance hands-on work with leadership responsibilities.\r\nCompensation Range\r\n$220,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.\r\nBenefits\r\nMedical, Dental, & Vision – 100% covered premiums.\r\nEquity – Stock Options.\r\n401(k) match.\r\nWFH Hardware.\r\nBolt is committed to building a diverse and inclusive environment in which we recognize and value each other's differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.\r\nJ-18808-Ljbffr","datePosted":"2026-08-08T01:59:22.243Z","dateModified":"2026-08-08T01:59:22.243Z","hiringOrganization":{"@type":"Organization","name":"Bolt Graphics","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"efde97b993dc48d449e6af4e"},"url":"https://jobsearcher.com/jobs/efde97b993dc48d449e6af4e"}}