{"schemaVersion":"jobsearcher.job.v1","id":"ee9f115baa091fa568804747","url":"https://jobsearcher.com/jobs/ee9f115baa091fa568804747","canonicalUrl":"https://jobsearcher.com/jobs/ee9f115baa091fa568804747","title":"Packaging Design Engineer","description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\n\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.\n\nTHE TEAM:\nThe AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.\n\nTHE ROLE:\nThe AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.\n\nTHE PERSON:\nThis is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.\n\nKEY RESPONSIBILITIES:\n\nUse Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.\n\nUse analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stagesand negotiate with chip/system teams on product specification.\n\nConduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc) for various device packaging.\n\nCollaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.\n\nDevelop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.\n\nCome up with performance metrics for organic package technologies in order to design high speed chips and systems.\n\nPerforming Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.\n\nDevelop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.\n\nPREFERRED EXPERIENCE:\n\nHave a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines.\n\nPackage/PCB layout experience. Experience in high power, Gbs IO products is a plus.\n\nCurrent working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.\n\nWorking knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.\n\nKnowledge on DoE, DFM/DFR is a plus.\n\nGood knowledge of SerDes design and package/PCB layout constraints.\n\nMentor junior package designers in the group.\n\nACADEMIC CREDENTIALS:\n\nBachelor’s or Master's degree in Engineering\n\nLOCATION:\nSan Jose, CA ; San Diego, CA\n\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\n\n#J-18808-Ljbffr","company":"Socket","rawCompany":"socket","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-02T03:34:01.863Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Packaging Design Engineer","description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\n\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.\n\nTHE TEAM:\nThe AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.\n\nTHE ROLE:\nThe AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.\n\nTHE PERSON:\nThis is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.\n\nKEY RESPONSIBILITIES:\n\nUse Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.\n\nUse analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stagesand negotiate with chip/system teams on product specification.\n\nConduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc) for various device packaging.\n\nCollaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.\n\nDevelop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.\n\nCome up with performance metrics for organic package technologies in order to design high speed chips and systems.\n\nPerforming Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.\n\nDevelop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.\n\nPREFERRED EXPERIENCE:\n\nHave a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines.\n\nPackage/PCB layout experience. Experience in high power, Gbs IO products is a plus.\n\nCurrent working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.\n\nWorking knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.\n\nKnowledge on DoE, DFM/DFR is a plus.\n\nGood knowledge of SerDes design and package/PCB layout constraints.\n\nMentor junior package designers in the group.\n\nACADEMIC CREDENTIALS:\n\nBachelor’s or Master's degree in Engineering\n\nLOCATION:\nSan Jose, CA ; San Diego, CA\n\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\n\n#J-18808-Ljbffr","datePosted":"2026-09-02T03:34:01.863Z","dateModified":"2026-09-02T03:34:01.863Z","hiringOrganization":{"@type":"Organization","name":"Socket","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"ee9f115baa091fa568804747"},"url":"https://jobsearcher.com/jobs/ee9f115baa091fa568804747"}}