{"schemaVersion":"jobsearcher.job.v1","id":"ed558844df336c41cb0f9df6","url":"https://jobsearcher.com/jobs/ed558844df336c41cb0f9df6","canonicalUrl":"https://jobsearcher.com/jobs/ed558844df336c41cb0f9df6","title":"Silicon Validation Engineer, Software","description":"About Etched\n\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\n\nJob Summary\n\nWe are seeking a skilled and motivated Silicon Validation Firmware Engineer to develop the firmware and low-level software that validates our AI/ML accelerator ASICs across their entire Lifecycle, from pre-silicon emulation and FPGA prototyping through post-silicon bring-up, characterization, and production ramp. In this role you will build the validation firmware, test content, and automation that prove our silicon works, and you will be hands-on debugging real hardware in the lab. Your work directly enables functional correctness, performance, and reliability of our cutting-edge products.\n\nKey Responsibilities\n\nDevelop and own low-level validation firmware in C/C++ that runs across emulation and physical silicon, providing test content pre-silicon and reusing it to drive post-silicon bring-up.\n\nDrive early bring-up of first silicon: boot, initialization, feature enablement, and debug of ASICs.\n\nPerform deep-dive debug of silicon issues spanning firmware, RTL, electrical, protocol, and system levels; root-cause and resolve failures.\n\nBuild firmware infrastructure including hardware abstraction layers (HALs) and low-level device drivers for compute units, memory subsystems, and high-speed interfaces.\n\nDevelop and extend validation automation, result-capture, and regression frameworks (CI/CD) to run validation at scale.\n\nAuthor firmware-driven test plans and define coverage metrics across IP blocks and subsystems; execute functional, performance, and stress/corner-case testing.\n\nValidate and characterize custom IP blocks and accelerator components on both pre- and post-silicon platforms.\n\nUse debug consoles and lab tooling (JTAG, UART, logic/protocol analyzers) for silicon debug and characterization.\n\nCollaborate closely with design, verification, architecture, DFT, and driver teams to ensure a smooth transition from pre-silicon verification to post-silicon validation, and to feed silicon issues back into revisions and firmware/driver workarounds.\n\nYou may be a good fit if you have (Must-have qualifications)\n\nProficiency in C/C++ for firmware and bare-metal development, plus Python for validation automation and scripting.\n\nUnderstanding of SoC/computer architecture (CPU cores, memory subsystems, caches, interconnects).\n\nSolid low-level/embedded fundamentals: bootloaders, hardware abstraction layers, device drivers, register/interrupt programming, and bare-metal or RTOS environments.\n\nKnowledge and familiarity developing and debugging in Linux environments.\n\nStrong problem-solving, analytical, and cross-functional collaboration skills across hardware and software teams.\n\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (Master's a plus).\n\nStrong candidates may also have experience with (Nice-to-have qualifications)\n\n2+ years of experience developing firmware / embedded software for ASICs or SoCs\n\nHands-on experience with silicon bring-up and low-level debug (boot, initialization, root-causing failures across firmware/electrical/protocol layers).\n\nExperience with JTAG and debuggers (e.g., Lauterbach/GDB) and serial/UART debug consoles.\n\nExperience across both pre-silicon (emulation, FPGA, RTL simulation) and post-silicon (lab bring-up, characterization) environments.\n\nExperience with one or more high-speed interfaces: PCIe, DDR/LPDDR/HBM, SerDes, or die-to-die / chiplet interconnect.\n\nExperience building test/validation automation and regression frameworks (CI/CD).\n\nRTOS experience (FreeRTOS, Zephyr, NuttX) or RISC-V firmware development.\n\nFamiliarity with platform/system firmware (UEFI, ACPI, BMC, BIOS).\n\nAbility to read RTL (Verilog/SystemVerilog) and debug in simulation.\n\nHands-on lab instrumentation experience (oscilloscopes, logic/protocol analyzers, BERTs) and signal-integrity awareness.\n\nBenefits\n\nMedical, dental, and vision packages with generous premium coverage\n\n$500 per month credit for waiving medical benefits\n\nHousing subsidy of $2k per month for those living within walking distance of the office\n\nRelocation support for those moving to San Jose (Santana Row)\n\nVarious wellness benefits covering fitness, mental health, and more\n\nDaily lunch and dinner in our office\n\nUnlimited compute budget subject to ROI justification\n\nHow we’re different\n\nEtched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.\n\nWe are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.","company":"Etched","rawCompany":"etched","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-04T08:24:07.423Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1252.00","title":"Software Developers","slug":"software-developers"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"513210","title":"Software Publishers","slug":"software-publishers"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Silicon Validation Engineer, Software","description":"About Etched\n\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\n\nJob Summary\n\nWe are seeking a skilled and motivated Silicon Validation Firmware Engineer to develop the firmware and low-level software that validates our AI/ML accelerator ASICs across their entire Lifecycle, from pre-silicon emulation and FPGA prototyping through post-silicon bring-up, characterization, and production ramp. In this role you will build the validation firmware, test content, and automation that prove our silicon works, and you will be hands-on debugging real hardware in the lab. Your work directly enables functional correctness, performance, and reliability of our cutting-edge products.\n\nKey Responsibilities\n\nDevelop and own low-level validation firmware in C/C++ that runs across emulation and physical silicon, providing test content pre-silicon and reusing it to drive post-silicon bring-up.\n\nDrive early bring-up of first silicon: boot, initialization, feature enablement, and debug of ASICs.\n\nPerform deep-dive debug of silicon issues spanning firmware, RTL, electrical, protocol, and system levels; root-cause and resolve failures.\n\nBuild firmware infrastructure including hardware abstraction layers (HALs) and low-level device drivers for compute units, memory subsystems, and high-speed interfaces.\n\nDevelop and extend validation automation, result-capture, and regression frameworks (CI/CD) to run validation at scale.\n\nAuthor firmware-driven test plans and define coverage metrics across IP blocks and subsystems; execute functional, performance, and stress/corner-case testing.\n\nValidate and characterize custom IP blocks and accelerator components on both pre- and post-silicon platforms.\n\nUse debug consoles and lab tooling (JTAG, UART, logic/protocol analyzers) for silicon debug and characterization.\n\nCollaborate closely with design, verification, architecture, DFT, and driver teams to ensure a smooth transition from pre-silicon verification to post-silicon validation, and to feed silicon issues back into revisions and firmware/driver workarounds.\n\nYou may be a good fit if you have (Must-have qualifications)\n\nProficiency in C/C++ for firmware and bare-metal development, plus Python for validation automation and scripting.\n\nUnderstanding of SoC/computer architecture (CPU cores, memory subsystems, caches, interconnects).\n\nSolid low-level/embedded fundamentals: bootloaders, hardware abstraction layers, device drivers, register/interrupt programming, and bare-metal or RTOS environments.\n\nKnowledge and familiarity developing and debugging in Linux environments.\n\nStrong problem-solving, analytical, and cross-functional collaboration skills across hardware and software teams.\n\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (Master's a plus).\n\nStrong candidates may also have experience with (Nice-to-have qualifications)\n\n2+ years of experience developing firmware / embedded software for ASICs or SoCs\n\nHands-on experience with silicon bring-up and low-level debug (boot, initialization, root-causing failures across firmware/electrical/protocol layers).\n\nExperience with JTAG and debuggers (e.g., Lauterbach/GDB) and serial/UART debug consoles.\n\nExperience across both pre-silicon (emulation, FPGA, RTL simulation) and post-silicon (lab bring-up, characterization) environments.\n\nExperience with one or more high-speed interfaces: PCIe, DDR/LPDDR/HBM, SerDes, or die-to-die / chiplet interconnect.\n\nExperience building test/validation automation and regression frameworks (CI/CD).\n\nRTOS experience (FreeRTOS, Zephyr, NuttX) or RISC-V firmware development.\n\nFamiliarity with platform/system firmware (UEFI, ACPI, BMC, BIOS).\n\nAbility to read RTL (Verilog/SystemVerilog) and debug in simulation.\n\nHands-on lab instrumentation experience (oscilloscopes, logic/protocol analyzers, BERTs) and signal-integrity awareness.\n\nBenefits\n\nMedical, dental, and vision packages with generous premium coverage\n\n$500 per month credit for waiving medical benefits\n\nHousing subsidy of $2k per month for those living within walking distance of the office\n\nRelocation support for those moving to San Jose (Santana Row)\n\nVarious wellness benefits covering fitness, mental health, and more\n\nDaily lunch and dinner in our office\n\nUnlimited compute budget subject to ROI justification\n\nHow we’re different\n\nEtched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.\n\nWe are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.","datePosted":"2026-09-04T08:24:07.423Z","dateModified":"2026-09-04T08:24:07.423Z","hiringOrganization":{"@type":"Organization","name":"Etched","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"ed558844df336c41cb0f9df6"},"url":"https://jobsearcher.com/jobs/ed558844df336c41cb0f9df6"}}