{"schemaVersion":"jobsearcher.job.v1","id":"ecbb14e155be73a6b3d1c803","url":"https://jobsearcher.com/jobs/ecbb14e155be73a6b3d1c803","canonicalUrl":"https://jobsearcher.com/jobs/ecbb14e155be73a6b3d1c803","title":"Lead Embedded CPU PPA Architect","description":"Overview:\nADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\n\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.\nResponsibilities:\nTHE ROLE:\nWe are seeking a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.\n\nTHE PERSON:\nYou will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones.\n\nKEY RESPONSIBILITIES:\n\nAlign Product Requirements with Cores IP\nDrive alignment on usage model (Product Lifetime, % residency in different CPU operating states, etc.), and operating condition constraints (Min/max ambient/case temp, TDC/EDC, customer-specific failure rate specs, etc.) as it impact achievable performance at power.\nDrive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements.\nDrive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements.\nTranslate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.\nDrive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams.\nDrive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition.\nBounding Box / Targets / Program Readiness\nDrive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).\nOwn a structured “open items” closure mechanism for performance and power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.\nTight Partnership with Cores Power & Performance Modeling\nPartner closely with the power & performance modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.\nConsume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.\nTight Partnership with Cores Advanced Methodology team\nPartner closely with Cores power delivery, thermals, and reliability technical leads to ensure the highly aggressive operating targets are met while simultaneously delivering high performance CPU products.\nProvide critical feedback to Embedded BU in these technical areas around SoC, package, and platform design to ensure reliable and robust operation.\n\nKEY RESPONSIBILITIES\nStrong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system driven constraints.\nWorking knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.\nWorking knowledge of device and system reliability requirements, and thermal management algorithms.\nDemonstrated ability to lead complex cross‑functional execution (architecture FW/BIOS validation\npackage/platform).\nFamiliarity collaborating with pre‑silicon power & performance modeling teams and aligning architecture assumptions/targets with projections.\nExperience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).\n\nACADEMIC CREDENTIALS\nBS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience.\n\nLOCATION:\nSanta Clara, CA\n\n#LI-SL2\n#LI-HYBRID\nQualifications:\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","company":"Advanced Micro Devices","rawCompany":"advanced micro devices","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-06T14:23:00.287Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"11-9041.00","title":"Architectural and Engineering Managers","slug":"architectural-and-engineering-managers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"513210","title":"Software Publishers","slug":"software-publishers"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Lead Embedded CPU PPA Architect","description":"Overview:\nADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\n\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.\nResponsibilities:\nTHE ROLE:\nWe are seeking a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management.\n\nTHE PERSON:\nYou will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones.\n\nKEY RESPONSIBILITIES:\n\nAlign Product Requirements with Cores IP\nDrive alignment on usage model (Product Lifetime, % residency in different CPU operating states, etc.), and operating condition constraints (Min/max ambient/case temp, TDC/EDC, customer-specific failure rate specs, etc.) as it impact achievable performance at power.\nDrive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements.\nDrive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements.\nTranslate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.\nDrive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams.\nDrive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition.\nBounding Box / Targets / Program Readiness\nDrive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).\nOwn a structured “open items” closure mechanism for performance and power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.\nTight Partnership with Cores Power & Performance Modeling\nPartner closely with the power & performance modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.\nConsume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.\nTight Partnership with Cores Advanced Methodology team\nPartner closely with Cores power delivery, thermals, and reliability technical leads to ensure the highly aggressive operating targets are met while simultaneously delivering high performance CPU products.\nProvide critical feedback to Embedded BU in these technical areas around SoC, package, and platform design to ensure reliable and robust operation.\n\nKEY RESPONSIBILITIES\nStrong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system driven constraints.\nWorking knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.\nWorking knowledge of device and system reliability requirements, and thermal management algorithms.\nDemonstrated ability to lead complex cross‑functional execution (architecture FW/BIOS validation\npackage/platform).\nFamiliarity collaborating with pre‑silicon power & performance modeling teams and aligning architecture assumptions/targets with projections.\nExperience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).\n\nACADEMIC CREDENTIALS\nBS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience.\n\nLOCATION:\nSanta Clara, CA\n\n#LI-SL2\n#LI-HYBRID\nQualifications:\nBenefits offered are described: AMD benefits at a glance.\n\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\n\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","datePosted":"2026-08-06T14:23:00.287Z","dateModified":"2026-08-06T14:23:00.287Z","hiringOrganization":{"@type":"Organization","name":"Advanced Micro Devices","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"ecbb14e155be73a6b3d1c803"},"url":"https://jobsearcher.com/jobs/ecbb14e155be73a6b3d1c803"}}