{"schemaVersion":"jobsearcher.job.v1","id":"e2bf74baf997b85edc90d739","url":"https://jobsearcher.com/jobs/e2bf74baf997b85edc90d739","canonicalUrl":"https://jobsearcher.com/jobs/e2bf74baf997b85edc90d739","title":"Design Verification Engineer","description":"Job DescriptionAbout the role: Design Verification engineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.Build power/perf dashboard for tracking and publishingDebug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.Contribute to automation of verification/regression and power/performance measurement flows (Python).Minimum QualificationsProven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).Working knowledge of RTL design principles and digital design fundamentals.Proficiency in Python (or Perl) scripting for automation.Preferred QualificationsExperience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).Formal verification and/or emulation (Palladium / Zebu) experience.Familiarity with the RTL-to-GDSII flow.Data analysis / ML approaches for coverage or debug triage.","company":"BCforward","rawCompany":"bcforward","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-06T10:23:03.429Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Verification Engineer","description":"Job DescriptionAbout the role: Design Verification engineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.ResponsibilitiesDevelop and execute verification plans for RTL blocks/IPs across the subsystem.Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.Drive functional coverage and assertion (SVA) closure; run and triage regressions.Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.Build power/perf dashboard for tracking and publishingDebug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.Contribute to automation of verification/regression and power/performance measurement flows (Python).Minimum QualificationsProven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).Working knowledge of RTL design principles and digital design fundamentals.Proficiency in Python (or Perl) scripting for automation.Preferred QualificationsExperience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).Formal verification and/or emulation (Palladium / Zebu) experience.Familiarity with the RTL-to-GDSII flow.Data analysis / ML approaches for coverage or debug triage.","datePosted":"2026-08-06T10:23:03.429Z","dateModified":"2026-08-06T10:23:03.429Z","hiringOrganization":{"@type":"Organization","name":"BCforward","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"e2bf74baf997b85edc90d739"},"url":"https://jobsearcher.com/jobs/e2bf74baf997b85edc90d739"}}