{"schemaVersion":"jobsearcher.job.v1","id":"de28f34d43c0b841e9039ce8","url":"https://jobsearcher.com/jobs/de28f34d43c0b841e9039ce8","canonicalUrl":"https://jobsearcher.com/jobs/de28f34d43c0b841e9039ce8","title":"I/O Design Engineer","description":"Overview\nIn this role you will contribute to the design and verification of a broad range of I/O and analog/mixed-signal IP for advanced nodes. You will work within Broadcom’s Central Engineering Group to shape silicon interfaces and performance across AI programs and customer products. You’ll tackle challenges in CMOS I/O, precision references, and power-on-reset circuits, while collaborating closely with layout teams and verification engineers. This position offers growth in a world-class, collaborative environment focused on cutting-edge silicon technologies. You will drive impact from design through silicon bring-up on high-performance IP blocks.\n\nCompensation / BenefitsMedical, dental and vision plans401(k) with company matchingEmployee Stock Purchase Program (ESPP)Employee Assistance Program (EAP)company paid holidayspaid sick leave and vacation time\nResponsibilitiesDesign CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuitsRun simulations to validate AC/DC performance, signal integrity, jitter and powerPerform transistor reliability and EMIR analysisCollaborate with layout teams to oversee physical design and verificationBuild Verilog, Synopsys Liberty and IBIS modelsCreate and maintain detailed technical documentation (datasheets, application notes, integration guides)Support chip-level integration and silicon bring-up in test chips and customer products\nKey requirementsMS or PhD in Electrical Engineering6+ years of I/O or analog circuit design experienceDeep proficiency in Cadence Virtuoso Schematic/Layout and SPICE/Spectre simulationsSolid foundation in I/O protocols (GPIO, I2C, I3C, eMMC, RGMII, SPMI)Familiarity with ESD, latch-up, EMI and Signal IntegrityExperience with advanced CMOS FinFET and GAA nodes, including PPA tradeoffscollaborative mindsetattention to detailstrong problem-solving abilitiesCadence VirtuosoSPICE/SpectreVerilog","company":"Broadcom","rawCompany":"broadcom","city":"Phoenix","state":"AZ","isRemote":false,"isActive":false,"createdAt":"2026-09-15T03:54:21.302Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334418","title":"Printed Circuit Assembly (Electronic Assembly) Manufacturing","slug":"printed-circuit-assembly-electronic-assembly-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"I/O Design Engineer","description":"Overview\nIn this role you will contribute to the design and verification of a broad range of I/O and analog/mixed-signal IP for advanced nodes. You will work within Broadcom’s Central Engineering Group to shape silicon interfaces and performance across AI programs and customer products. You’ll tackle challenges in CMOS I/O, precision references, and power-on-reset circuits, while collaborating closely with layout teams and verification engineers. This position offers growth in a world-class, collaborative environment focused on cutting-edge silicon technologies. You will drive impact from design through silicon bring-up on high-performance IP blocks.\n\nCompensation / BenefitsMedical, dental and vision plans401(k) with company matchingEmployee Stock Purchase Program (ESPP)Employee Assistance Program (EAP)company paid holidayspaid sick leave and vacation time\nResponsibilitiesDesign CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuitsRun simulations to validate AC/DC performance, signal integrity, jitter and powerPerform transistor reliability and EMIR analysisCollaborate with layout teams to oversee physical design and verificationBuild Verilog, Synopsys Liberty and IBIS modelsCreate and maintain detailed technical documentation (datasheets, application notes, integration guides)Support chip-level integration and silicon bring-up in test chips and customer products\nKey requirementsMS or PhD in Electrical Engineering6+ years of I/O or analog circuit design experienceDeep proficiency in Cadence Virtuoso Schematic/Layout and SPICE/Spectre simulationsSolid foundation in I/O protocols (GPIO, I2C, I3C, eMMC, RGMII, SPMI)Familiarity with ESD, latch-up, EMI and Signal IntegrityExperience with advanced CMOS FinFET and GAA nodes, including PPA tradeoffscollaborative mindsetattention to detailstrong problem-solving abilitiesCadence VirtuosoSPICE/SpectreVerilog","datePosted":"2026-09-15T03:54:21.302Z","dateModified":"2026-09-15T03:54:21.302Z","hiringOrganization":{"@type":"Organization","name":"Broadcom","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Phoenix","addressRegion":"AZ","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"de28f34d43c0b841e9039ce8"},"url":"https://jobsearcher.com/jobs/de28f34d43c0b841e9039ce8"}}