{"schemaVersion":"jobsearcher.job.v1","id":"d95bef9c55ce7e8ecbc2d255","url":"https://jobsearcher.com/jobs/d95bef9c55ce7e8ecbc2d255","canonicalUrl":"https://jobsearcher.com/jobs/d95bef9c55ce7e8ecbc2d255","title":"Intermediate Semiconductor Process Engineer","description":"Intermediate Semiconductor Process Engineer\nIntermediate Semiconductor Process Engineer needed for a 12‑month contract‑to‑hire opportunity with Yoh's client located in Santa Clara, California.\n\nPay Rate: $45 to $53 per hour\n\nTop Skills You Should Possess\n\nSolid interpersonal skills\n\nStrong analytical skills\n\nAbility to quickly adapt to change\n\nResponsibilities\n\nDesign, collect data, analyze and compile reports on process engineering experiments for defect reduction, within safety guidelines.\n\nTroubleshoot defect problems, perform Root Cause Analysis and resolve moderately difficult process engineering issues.\n\nImplement new technology, products and analytical instrumentation to support the defect study.\n\nDesign the failure analysis (FA) DOE for key defect critical components to troubleshoot wafer defect issues on R&D programs and major customer escalation.\n\nPerform the FA, collect and analyze data within safety guidelines.\n\nCommunicate FA observations and recommend solution paths in defect troubleshooting.\n\nMeasure wafer defect/film properties, organize data/reports for review to support defectivity improvement by SEM/FIB.\n\nPrepare wafers for experimentation, including cleaning, loading wafers, preparing klarf files; evaluate and recommend performance of process system.\n\nOperate scanning electron microscope (SEM) for top view or critical dimension and energy dispersive spectroscopy (EDS) analysis; identify patterns of interest and optimize conditions.\n\nPrepare samples for Focused Ion Beam (FIB) lamella making using Zeta Marking tool; optimize sample prep procedures and identify cutting location.\n\nOperate and check performance of equipment to perform sample prep process, under limited supervision.\n\nUnderstand SEM and FIB principles.\n\nOperate FIB for making TEM lamella when required; identify patterns of interest and optimize conditions.\n\nPerform SEM/FIB system software alignment functions; routine maintenance procedures (flash, plasma clean).\n\nPerform routine shutdown procedures; identify problems, put tool down and call for service.\n\nCoordinate instrument repair and maintenance; coordinate with engineering on wafer evaluations.\n\nOrder equipment and supplies; coordinate with vendors and purchasing.\n\nReport and communicate wafer defect analysis results; recommend solution paths for wafer defect troubleshooting on key R&D programs.\n\nInteract with vendors/suppliers to evaluate/troubleshoot latest defect metrology tools (SEM, EDX, FIB, wafer scribing).\n\nDevelop and publish best known method (BKM) procedures including sample prep, SEM conditions, and special sample handling.\n\nGenerate internal documentation for products, presentations and technical reports.\n\nLeadership & Training Responsibilities\n\nProvide trainings for junior engineers for wafer preparation/analysis on defect metrology tools.\n\nContribute and manage the metrology tool (Zeta/SEMVision) operation.\n\nInterface with requestors, understand detailed requirements, and communicate on results.\n\nHelp lab monitor wafer in process (WIP) and maintain quality, turnaround time, and throughput.\n\nDefine and forecast defect metrology tool requirements to support N+ defect requirement.\n\nPreferred Qualifications\n\nExperience in semiconductor industry: 1–2 years.\n\nMinimum two years of college (Associate's Degree).\n\nBenefits\n\nMedical, Dental & Vision Benefits (for employees working 20+ hours per week).\n\nHealth Savings Account (HSA) (for employees working 20+ hours per week).\n\nLife & Disability Insurance (for employees working 20+ hours per week).\n\nMetLife Voluntary Benefits.\n\nEmployee Assistance Program (EAP).\n\n401K Retirement Savings Plan.\n\nDirect Deposit & weekly e-payroll.\n\nReferral Bonus Programs.\n\nCertification and training opportunities.\n\nEqual Opportunity Employer\nYoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.\n\nFor California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.\n\nIt is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.\n\nBy applying and submitting your resume, you authorize Yoh to review and reformat your resume to meet Yoh's hiring clients' preferences. To learn more about Yoh's privacy practices, please see our Candidate Privacy Notice: https://www.yoh.com/privacy-notice\n\n#J-18808-Ljbffr","company":"Yoh","rawCompany":"yoh","city":"Santa Clara","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-06-20T04:44:22.338Z","occupations":[{"code":"51-9141.00","title":"Semiconductor Processing Technicians","slug":"semiconductor-processing-technicians"},{"code":"17-2199.06","title":"Microsystems Engineers","slug":"microsystems-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Intermediate Semiconductor Process Engineer","description":"Intermediate Semiconductor Process Engineer\nIntermediate Semiconductor Process Engineer needed for a 12‑month contract‑to‑hire opportunity with Yoh's client located in Santa Clara, California.\n\nPay Rate: $45 to $53 per hour\n\nTop Skills You Should Possess\n\nSolid interpersonal skills\n\nStrong analytical skills\n\nAbility to quickly adapt to change\n\nResponsibilities\n\nDesign, collect data, analyze and compile reports on process engineering experiments for defect reduction, within safety guidelines.\n\nTroubleshoot defect problems, perform Root Cause Analysis and resolve moderately difficult process engineering issues.\n\nImplement new technology, products and analytical instrumentation to support the defect study.\n\nDesign the failure analysis (FA) DOE for key defect critical components to troubleshoot wafer defect issues on R&D programs and major customer escalation.\n\nPerform the FA, collect and analyze data within safety guidelines.\n\nCommunicate FA observations and recommend solution paths in defect troubleshooting.\n\nMeasure wafer defect/film properties, organize data/reports for review to support defectivity improvement by SEM/FIB.\n\nPrepare wafers for experimentation, including cleaning, loading wafers, preparing klarf files; evaluate and recommend performance of process system.\n\nOperate scanning electron microscope (SEM) for top view or critical dimension and energy dispersive spectroscopy (EDS) analysis; identify patterns of interest and optimize conditions.\n\nPrepare samples for Focused Ion Beam (FIB) lamella making using Zeta Marking tool; optimize sample prep procedures and identify cutting location.\n\nOperate and check performance of equipment to perform sample prep process, under limited supervision.\n\nUnderstand SEM and FIB principles.\n\nOperate FIB for making TEM lamella when required; identify patterns of interest and optimize conditions.\n\nPerform SEM/FIB system software alignment functions; routine maintenance procedures (flash, plasma clean).\n\nPerform routine shutdown procedures; identify problems, put tool down and call for service.\n\nCoordinate instrument repair and maintenance; coordinate with engineering on wafer evaluations.\n\nOrder equipment and supplies; coordinate with vendors and purchasing.\n\nReport and communicate wafer defect analysis results; recommend solution paths for wafer defect troubleshooting on key R&D programs.\n\nInteract with vendors/suppliers to evaluate/troubleshoot latest defect metrology tools (SEM, EDX, FIB, wafer scribing).\n\nDevelop and publish best known method (BKM) procedures including sample prep, SEM conditions, and special sample handling.\n\nGenerate internal documentation for products, presentations and technical reports.\n\nLeadership & Training Responsibilities\n\nProvide trainings for junior engineers for wafer preparation/analysis on defect metrology tools.\n\nContribute and manage the metrology tool (Zeta/SEMVision) operation.\n\nInterface with requestors, understand detailed requirements, and communicate on results.\n\nHelp lab monitor wafer in process (WIP) and maintain quality, turnaround time, and throughput.\n\nDefine and forecast defect metrology tool requirements to support N+ defect requirement.\n\nPreferred Qualifications\n\nExperience in semiconductor industry: 1–2 years.\n\nMinimum two years of college (Associate's Degree).\n\nBenefits\n\nMedical, Dental & Vision Benefits (for employees working 20+ hours per week).\n\nHealth Savings Account (HSA) (for employees working 20+ hours per week).\n\nLife & Disability Insurance (for employees working 20+ hours per week).\n\nMetLife Voluntary Benefits.\n\nEmployee Assistance Program (EAP).\n\n401K Retirement Savings Plan.\n\nDirect Deposit & weekly e-payroll.\n\nReferral Bonus Programs.\n\nCertification and training opportunities.\n\nEqual Opportunity Employer\nYoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.\n\nFor California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.\n\nIt is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.\n\nBy applying and submitting your resume, you authorize Yoh to review and reformat your resume to meet Yoh's hiring clients' preferences. To learn more about Yoh's privacy practices, please see our Candidate Privacy Notice: https://www.yoh.com/privacy-notice\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T04:44:22.338Z","dateModified":"2026-06-20T04:44:22.338Z","hiringOrganization":{"@type":"Organization","name":"Yoh","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d95bef9c55ce7e8ecbc2d255"},"url":"https://jobsearcher.com/jobs/d95bef9c55ce7e8ecbc2d255"}}