{"schemaVersion":"jobsearcher.job.v1","id":"d8e2c5fb90a5b973e89d093e","url":"https://jobsearcher.com/jobs/d8e2c5fb90a5b973e89d093e","canonicalUrl":"https://jobsearcher.com/jobs/d8e2c5fb90a5b973e89d093e","title":"Software Engineer","description":"PCIe Protocol IP Verification Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the ASIC Verification domain. Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches. IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up. Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers Virtusa is looking for PCIe protocol experts to integrate the 3rd Party IP's [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.Job DescriptionApplication or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification. Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level .SkillsRequirementsDigital design with system verilog RTL coding at IP/System Integration level. Experience with one of the simulators like Questa , VCS & Xelium. Ability to put together top level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required. Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification. Knowledge of Python, C/Perl scripting is required. Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps. Understand the configurations of all Generations of PCIe combinations for debugging the failures.Job SummaryJob number: CREQ266437Profession: OtherExperience: 2","company":"Virtusa","rawCompany":"virtusa","city":"Millbrae","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-09-13T05:27:16.631Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"15-1252.00","title":"Software Developers","slug":"software-developers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Software Engineer","description":"PCIe Protocol IP Verification Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the ASIC Verification domain. Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches. IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up. Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers Virtusa is looking for PCIe protocol experts to integrate the 3rd Party IP's [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.Job DescriptionApplication or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification. Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level .SkillsRequirementsDigital design with system verilog RTL coding at IP/System Integration level. Experience with one of the simulators like Questa , VCS & Xelium. Ability to put together top level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required. Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification. Knowledge of Python, C/Perl scripting is required. Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps. Understand the configurations of all Generations of PCIe combinations for debugging the failures.Job SummaryJob number: CREQ266437Profession: OtherExperience: 2","datePosted":"2026-09-13T05:27:16.631Z","dateModified":"2026-09-13T05:27:16.631Z","hiringOrganization":{"@type":"Organization","name":"Virtusa","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Millbrae","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d8e2c5fb90a5b973e89d093e"},"url":"https://jobsearcher.com/jobs/d8e2c5fb90a5b973e89d093e"}}