{"schemaVersion":"jobsearcher.job.v1","id":"d5cf779b68ee415ad8b2e770","url":"https://jobsearcher.com/jobs/d5cf779b68ee415ad8b2e770","canonicalUrl":"https://jobsearcher.com/jobs/d5cf779b68ee415ad8b2e770","title":"Design Engineer - AI SoC Development","description":"Job Details\nJob Description: Join Intel’s AI Revolution. Intel’s AI SoC organization develops cutting‑edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast‑paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.\n\nWhat You’ll Do\nAs an RTL Design Engineer, you’ll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoC or discrete component designs. You’ll participate in defining architecture and microarchitecture features while performing quality checks across various logic design aspects from RTL to timing/power convergence. You’ll apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you’ll review verification plans and resolve failing RTL tests to ensure feature correctness. You’ll follow secure development practices and collaborate with IP providers for SoC‑level integration and validation.\n\nKey Responsibilities\nArchitecture & Design\n\nContribute to evaluation of architectural trade‑offs considering features, performance, and system constraints\n\nImplement RTL in Verilog/System Verilog based on defined micro‑architecture\n\nIntegrate IP blocks at top level and ensure synthesis‑ and timing‑clean design\n\nVerification & Validation\n\nWork closely with verification teams to achieve full coverage and robust validation\n\nDevelop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks\n\nSupport silicon bring‑up and post‑silicon validation activities, including debug and performance analysis\n\nCollaboration & Quality\n\nCollaborate with senior engineers to adopt best practices and improve design methodologies\n\nDrive quality assurance compliance for smooth IP/SoC handoff\n\nWork with IP providers to integrate and validate IPs at the SoC level\n\nMinimum Qualifications\n\nBachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science\n\n4+ years of experience in/with:\n\nRTL design and implementation for ASIC/SoC development\n\nProficiency in Verilog/System Verilog for RTL coding and design\n\nExperience with synthesis tools and timing closure methodologies\n\nPreferred Qualifications\n\nUnderstanding of clock domain crossings, power optimization, and timing closure\n\nExposure to SoC system integration and CPU subsystem design\n\nFamiliarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures\n\nKnowledge of high‑speed and low‑power design techniques\n\nExperience with static timing analysis (STA) tools and methodologies\n\nHands‑on experience with formal verification tools and techniques\n\nBasic scripting skills (Python, TCL, etc.) for automation\n\nExperience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools\n\nAbility to work in a dynamic environment and adapt to changing requirements\n\nStrong problem‑solving skills, collaborative mindset, and eagerness to learn\n\nJob Type\nExperienced Hire\n\nShift\nShift 1 (United States of America)\n\nPrimary Location\nUS, California, Folsom\n\nAdditional Locations\nUS, California, Santa Clara; US, Oregon, Hillsboro; US, Texas, Austin\n\nPosting Statement\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\nPosition of Trust\nN/A\n\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\n\nAnnual Salary Range for jobs which could be performed in the US\n$164,470.00 - 232,190.00 USD\n\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.\n\nADDITIONAL INFORMATION\nIntel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.\n\n#J-18808-Ljbffr","company":"Intel","rawCompany":"intel","city":"Folsom","state":"CA","isRemote":false,"isActive":true,"createdAt":"2026-06-20T03:40:27.451Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Engineer - AI SoC Development","description":"Job Details\nJob Description: Join Intel’s AI Revolution. Intel’s AI SoC organization develops cutting‑edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast‑paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.\n\nWhat You’ll Do\nAs an RTL Design Engineer, you’ll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoC or discrete component designs. You’ll participate in defining architecture and microarchitecture features while performing quality checks across various logic design aspects from RTL to timing/power convergence. You’ll apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you’ll review verification plans and resolve failing RTL tests to ensure feature correctness. You’ll follow secure development practices and collaborate with IP providers for SoC‑level integration and validation.\n\nKey Responsibilities\nArchitecture & Design\n\nContribute to evaluation of architectural trade‑offs considering features, performance, and system constraints\n\nImplement RTL in Verilog/System Verilog based on defined micro‑architecture\n\nIntegrate IP blocks at top level and ensure synthesis‑ and timing‑clean design\n\nVerification & Validation\n\nWork closely with verification teams to achieve full coverage and robust validation\n\nDevelop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks\n\nSupport silicon bring‑up and post‑silicon validation activities, including debug and performance analysis\n\nCollaboration & Quality\n\nCollaborate with senior engineers to adopt best practices and improve design methodologies\n\nDrive quality assurance compliance for smooth IP/SoC handoff\n\nWork with IP providers to integrate and validate IPs at the SoC level\n\nMinimum Qualifications\n\nBachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science\n\n4+ years of experience in/with:\n\nRTL design and implementation for ASIC/SoC development\n\nProficiency in Verilog/System Verilog for RTL coding and design\n\nExperience with synthesis tools and timing closure methodologies\n\nPreferred Qualifications\n\nUnderstanding of clock domain crossings, power optimization, and timing closure\n\nExposure to SoC system integration and CPU subsystem design\n\nFamiliarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures\n\nKnowledge of high‑speed and low‑power design techniques\n\nExperience with static timing analysis (STA) tools and methodologies\n\nHands‑on experience with formal verification tools and techniques\n\nBasic scripting skills (Python, TCL, etc.) for automation\n\nExperience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools\n\nAbility to work in a dynamic environment and adapt to changing requirements\n\nStrong problem‑solving skills, collaborative mindset, and eagerness to learn\n\nJob Type\nExperienced Hire\n\nShift\nShift 1 (United States of America)\n\nPrimary Location\nUS, California, Folsom\n\nAdditional Locations\nUS, California, Santa Clara; US, Oregon, Hillsboro; US, Texas, Austin\n\nPosting Statement\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\n\nPosition of Trust\nN/A\n\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\n\nAnnual Salary Range for jobs which could be performed in the US\n$164,470.00 - 232,190.00 USD\n\nWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.\n\nADDITIONAL INFORMATION\nIntel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T03:40:27.451Z","dateModified":"2026-06-20T03:40:27.451Z","hiringOrganization":{"@type":"Organization","name":"Intel","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Folsom","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d5cf779b68ee415ad8b2e770"},"url":"https://jobsearcher.com/jobs/d5cf779b68ee415ad8b2e770"}}