{"schemaVersion":"jobsearcher.job.v1","id":"d4fb316e9eaa03e00a72b3f0","url":"https://jobsearcher.com/jobs/d4fb316e9eaa03e00a72b3f0","canonicalUrl":"https://jobsearcher.com/jobs/d4fb316e9eaa03e00a72b3f0","title":"Design Verification Engineer","description":"*Title: Design Verification Engineer (GPU) *\n\n*Location: San Jose Ca – Hybrid 3 days in office*\n\n*Duration: 6 Months *\n\n*Job Description:*\n\nAs a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.\n\nRole and Responsibilities:\n\n• Work with architects and designers to build verification environments and test plans\n\n• Craft functional verification coverage strategy to ensure complete test suite implementation\n\n• Develop assertions and checks to optimize isolation time and produce meaningful failing signatures\n\n• Analyze failing tests to root cause along, working with RTL and reference modeling teams\n\n• Provide input on Architectural and Micro-Architectural specifications for testability and accuracy\n\n• Examine code coverage results, identifying exclusions and improving stimulus\n\n• Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics\n\nSkills and Qualifications:\n\n• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role\n\n• Proficient in System Verilog/UVM/OVM, and OOP/C++\n\n• Deep understanding of constrained randomization and the development of efficient test suites\n\n• Experience with code coverage and functional coverage-driven verification methodology.\n\n• Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.\n\n• Working knowledge of scripting languages such as Python or Perl\n\n• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications:\n\n• MS CE/EE with 5+ years of industry experience in verification\n\n• Good verbal and written communication skills\n\n• Experience of GPU or CPU is a plus\n\nJob Type: Contract\n\nPay: $70.00 - $100.00 per hour\n\nSchedule:\n* 8 hour shift\n\nWork Location: In person","company":"Vedainfo","rawCompany":"vedainfo","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-04T08:52:50.102Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Verification Engineer","description":"*Title: Design Verification Engineer (GPU) *\n\n*Location: San Jose Ca – Hybrid 3 days in office*\n\n*Duration: 6 Months *\n\n*Job Description:*\n\nAs a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.\n\nRole and Responsibilities:\n\n• Work with architects and designers to build verification environments and test plans\n\n• Craft functional verification coverage strategy to ensure complete test suite implementation\n\n• Develop assertions and checks to optimize isolation time and produce meaningful failing signatures\n\n• Analyze failing tests to root cause along, working with RTL and reference modeling teams\n\n• Provide input on Architectural and Micro-Architectural specifications for testability and accuracy\n\n• Examine code coverage results, identifying exclusions and improving stimulus\n\n• Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics\n\nSkills and Qualifications:\n\n• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role\n\n• Proficient in System Verilog/UVM/OVM, and OOP/C++\n\n• Deep understanding of constrained randomization and the development of efficient test suites\n\n• Experience with code coverage and functional coverage-driven verification methodology.\n\n• Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.\n\n• Working knowledge of scripting languages such as Python or Perl\n\n• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications:\n\n• MS CE/EE with 5+ years of industry experience in verification\n\n• Good verbal and written communication skills\n\n• Experience of GPU or CPU is a plus\n\nJob Type: Contract\n\nPay: $70.00 - $100.00 per hour\n\nSchedule:\n* 8 hour shift\n\nWork Location: In person","datePosted":"2026-09-04T08:52:50.102Z","dateModified":"2026-09-04T08:52:50.102Z","hiringOrganization":{"@type":"Organization","name":"Vedainfo","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d4fb316e9eaa03e00a72b3f0"},"url":"https://jobsearcher.com/jobs/d4fb316e9eaa03e00a72b3f0"}}