{"schemaVersion":"jobsearcher.job.v1","id":"d4ae3a5e50fe97d9ca554c7c","url":"https://jobsearcher.com/jobs/d4ae3a5e50fe97d9ca554c7c","canonicalUrl":"https://jobsearcher.com/jobs/d4ae3a5e50fe97d9ca554c7c","title":"Design Verification Engineer","description":"Design Verification EngineerLocation: Bay Area (Day1 onsite preferable)Client: Google, Facebook, Cisco, Intel Mandatory: UVM minimum 3 years of experience also share a write up along with the submissionMust be proficient with:Building a test bench for a block using System Verilog and UVMWriting random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.Developing, maintaining and supporting of the UVM verification environment.Debugging tests with design engineers to deliver functionally correct design blocksWriting & analyzing functional coverage, assertionsGenerating and analyzing code coverage & writing waivers.Thanks & Regards,Akhil Reddy VontelaSoftware Technology Inc100 Overlook Center, Suite 200 Princeton, NJ 08540.Email: Akhil.reddy@stiorg.comContact: 6096697444","company":"Software Technology","rawCompany":"software technology","city":"Millbrae","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-07-14T00:37:20.476Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"15-1252.00","title":"Software Developers","slug":"software-developers"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541511","title":"Custom Computer Programming Services","slug":"custom-computer-programming-services"},{"code":"541330","title":"Engineering Services","slug":"engineering-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Design Verification Engineer","description":"Design Verification EngineerLocation: Bay Area (Day1 onsite preferable)Client: Google, Facebook, Cisco, Intel Mandatory: UVM minimum 3 years of experience also share a write up along with the submissionMust be proficient with:Building a test bench for a block using System Verilog and UVMWriting random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.Developing, maintaining and supporting of the UVM verification environment.Debugging tests with design engineers to deliver functionally correct design blocksWriting & analyzing functional coverage, assertionsGenerating and analyzing code coverage & writing waivers.Thanks & Regards,Akhil Reddy VontelaSoftware Technology Inc100 Overlook Center, Suite 200 Princeton, NJ 08540.Email: Akhil.reddy@stiorg.comContact: 6096697444","datePosted":"2026-07-14T00:37:20.476Z","dateModified":"2026-07-14T00:37:20.476Z","hiringOrganization":{"@type":"Organization","name":"Software Technology","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Millbrae","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d4ae3a5e50fe97d9ca554c7c"},"url":"https://jobsearcher.com/jobs/d4ae3a5e50fe97d9ca554c7c"}}