{"schemaVersion":"jobsearcher.job.v1","id":"d43af0ce68e08620ed5a28c9","url":"https://jobsearcher.com/jobs/d43af0ce68e08620ed5a28c9","canonicalUrl":"https://jobsearcher.com/jobs/d43af0ce68e08620ed5a28c9","title":"CPU Performance Architect","description":"Overview\nIn this role you will lead microarchitectural analysis on silicon to identify stalls, memory bottlenecks, and inefficiencies, driving root-cause resolution. You will design and run advanced power and performance experiments on physical silicon to validate pre-silicon projections against real hardware across general-purpose and AI/ML workloads. You’ll build early power and performance models to explore architectural scenarios and enable hardware-software co-optimization. Collaborating with lead CPU architects, you help set realistic power and performance goals for Google's future silicon, contributing to impactful products at scale.\n\nCompensation / Benefitsbonus targetequitybenefits\nResponsibilitiesLead deep-dive microarchitectural analysis to isolate stalls and bottlenecksDesign, build, and run power and performance experiments on physical siliconDevelop and maintain early-stage power and performance models for what-if scenariosPartner with CPU architects and cross-functional teams to define dynamic power and performance goalsContribute to hardware-software co-optimization and future silicon initiatives\nKey requirementsBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field8 years of experience with performance analysis, bottleneck isolation, and workload characterizationExperience with C/C++ for architectural modeling and Python for data analysis and automationCollaborative cross-functional collaborationStrong analytical and problem-solving abilitiesEffective communication of complex findings to technical and non-technical stakeholdersC/C++ for architectural modelingPython for data analysis and automationMicroarchitectural analysis and workload characterization","company":"Google","rawCompany":"google","city":"San Jose","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-09-15T03:33:00.788Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"CPU Performance Architect","description":"Overview\nIn this role you will lead microarchitectural analysis on silicon to identify stalls, memory bottlenecks, and inefficiencies, driving root-cause resolution. You will design and run advanced power and performance experiments on physical silicon to validate pre-silicon projections against real hardware across general-purpose and AI/ML workloads. You’ll build early power and performance models to explore architectural scenarios and enable hardware-software co-optimization. Collaborating with lead CPU architects, you help set realistic power and performance goals for Google's future silicon, contributing to impactful products at scale.\n\nCompensation / Benefitsbonus targetequitybenefits\nResponsibilitiesLead deep-dive microarchitectural analysis to isolate stalls and bottlenecksDesign, build, and run power and performance experiments on physical siliconDevelop and maintain early-stage power and performance models for what-if scenariosPartner with CPU architects and cross-functional teams to define dynamic power and performance goalsContribute to hardware-software co-optimization and future silicon initiatives\nKey requirementsBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field8 years of experience with performance analysis, bottleneck isolation, and workload characterizationExperience with C/C++ for architectural modeling and Python for data analysis and automationCollaborative cross-functional collaborationStrong analytical and problem-solving abilitiesEffective communication of complex findings to technical and non-technical stakeholdersC/C++ for architectural modelingPython for data analysis and automationMicroarchitectural analysis and workload characterization","datePosted":"2026-09-15T03:33:00.788Z","dateModified":"2026-09-15T03:33:00.788Z","hiringOrganization":{"@type":"Organization","name":"Google","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Jose","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d43af0ce68e08620ed5a28c9"},"url":"https://jobsearcher.com/jobs/d43af0ce68e08620ed5a28c9"}}