{"schemaVersion":"jobsearcher.job.v1","id":"d0f080af50c4946c78eff6a5","url":"https://jobsearcher.com/jobs/d0f080af50c4946c78eff6a5","canonicalUrl":"https://jobsearcher.com/jobs/d0f080af50c4946c78eff6a5","title":"Hardware Verification Engineer","description":"Job Description for DFT DV Engineer\r\nThe ideal candidate will work with multi-functional global teams to verify IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server processor products. Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. The ideal candidate will lead verification of high-performance microprocessors. The candidate is able to work with third party IP. You will develop system level and unit level test plans and test benches for verification of high speed D2D interfaces for UCIe hardware. You will write test benches using System Verilog and UVM.\r\nVerify high speed IOBIST interfaces for UCIe test functionality for high performance multi core server class processor.\r\nCreate test plans for unit-level and chip-level verification.\r\nDesign and implement test benches and verification environments.\r\nGenerate test patterns for ATE, debug failures, Yield analysis and evaluate coverage of design. and generate patterns for ATE.Required Skill:\r\n5 to 8 years of Hardware verification experience\r\nHave experience building agents, scoreboards and transactors from scratch\r\nGood knowledge of high performance microprocessor architecture\r\nUnderstanding of verification methodologyRequired Skills:4 to 6 years of experience\r\nExperience in Scan insertion with compression for Stuck-At and At-Speed test.\r\nExperience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug\r\nExperience in MBIST insertion, simulation and debug on RTL and gates netlist\r\nExperience in Boundary Scan insertion, simulation and verification.\r\nHands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)\r\nGood written and verbal communication skills in English\r\nSTA DFT Test mode timing constraint development and analysis is a plus\r\nKnowledge of Verilog HDL and experience with simulators and waveform debugging tools\r\nExperience with ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data a plus.","company":"Techdoquest","rawCompany":"techdoquest","city":"Santa Clara","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-04-23T01:14:05.728Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"15-1253.00","title":"Software Quality Assurance Analysts and Testers","slug":"software-quality-assurance-analysts-and-testers"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Hardware Verification Engineer","description":"Job Description for DFT DV Engineer\r\nThe ideal candidate will work with multi-functional global teams to verify IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server processor products. Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. The ideal candidate will lead verification of high-performance microprocessors. The candidate is able to work with third party IP. You will develop system level and unit level test plans and test benches for verification of high speed D2D interfaces for UCIe hardware. You will write test benches using System Verilog and UVM.\r\nVerify high speed IOBIST interfaces for UCIe test functionality for high performance multi core server class processor.\r\nCreate test plans for unit-level and chip-level verification.\r\nDesign and implement test benches and verification environments.\r\nGenerate test patterns for ATE, debug failures, Yield analysis and evaluate coverage of design. and generate patterns for ATE.Required Skill:\r\n5 to 8 years of Hardware verification experience\r\nHave experience building agents, scoreboards and transactors from scratch\r\nGood knowledge of high performance microprocessor architecture\r\nUnderstanding of verification methodologyRequired Skills:4 to 6 years of experience\r\nExperience in Scan insertion with compression for Stuck-At and At-Speed test.\r\nExperience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug\r\nExperience in MBIST insertion, simulation and debug on RTL and gates netlist\r\nExperience in Boundary Scan insertion, simulation and verification.\r\nHands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)\r\nGood written and verbal communication skills in English\r\nSTA DFT Test mode timing constraint development and analysis is a plus\r\nKnowledge of Verilog HDL and experience with simulators and waveform debugging tools\r\nExperience with ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data a plus.","datePosted":"2026-04-23T01:14:05.728Z","dateModified":"2026-04-23T01:14:05.728Z","hiringOrganization":{"@type":"Organization","name":"Techdoquest","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"d0f080af50c4946c78eff6a5"},"url":"https://jobsearcher.com/jobs/d0f080af50c4946c78eff6a5"}}