{"schemaVersion":"jobsearcher.job.v1","id":"cdd5a7bd688dc08d9618da94","url":"https://jobsearcher.com/jobs/cdd5a7bd688dc08d9618da94","canonicalUrl":"https://jobsearcher.com/jobs/cdd5a7bd688dc08d9618da94","title":"Systems Architect: Memory Wall Exploration","description":"This job is with HP, an inclusive employer and a member of myGwork – the largest global platform for the LGBTQ+ business community. Please do not contact the recruiter directly.\r\nSystems Architect: Memory Wall Exploration\r\nDescription -\r\nJob Summary:\r\nTheSystems Architect: Memory Wall Explorationfocuses on understanding how AI execution interacts with platform resources, particularly memory hierarchy, data movement, and shared-memory behavior across heterogeneous compute environments (CPU, GPU, AI accelerators). The architect will engage with internal teams and external partners (including memory and silicon vendors) to translate low-level technical characteristics into system-level guidance and platform strategy for HP.\r\nKey ResponsibilitiesPlatform Performance & Memory Analysis\r\nAnalyze how AI workloads interact with system resources across CPU, GPU, and AI acceleratorsEvaluate the impact ofmemory bandwidth, latency, contention, and data movementon workload performance, responsiveness, and power efficiencyCharacterize workload behavior inshared-memory systems, including interactions between foreground and background activityIdentify sources of performance variability and experience degradation under real-world multitasking scenarios.Overcome the performance bottleneck where processor speeds outpace memory bandwidth, focusing on optimizing data movement between CPUs, GPUs, and memory (DRAM, HBM, CXL).System-Level Guidance & Strategy\r\nTranslate memory and system-level constraints intoactionable guidancefor platformarchitecture, runtime, power, and performance teamsHelp define execution envelopes and tradeoffs (e.g., placement, concurrency limits, configuration sensitivity) that improve AI experience predictabilityContribute toplatform-level strategyby connecting technical constraints to user experience outcomes and product decisionsCross-Functional & Ecosystem Collaboration\r\nWork closely with platform architecture, runtime, power/thermal, and AI enablement teams within HPEngage with external ecosystem partners, including memory and silicon vendors, to:\r\nUnderstand platform capabilities, tradeoffs, and roadmap directionsEvaluate how memory technologies and configurations affect real-world AI experiencesTranslate partner insights intoHP-specific system guidance and strategic recommendationsSupport technical alignment discussionsPlatform Enablement\r\nAssist in defining internal tools, metrics, and evaluation methods for assessing AI workload behavior and memory sensitivityContribute to documentation, best practices, and internal frameworks related to system-level AI performanceHelp scale AI experiences across a diverse portfolio of devices and SKUsQualificationsEducation:M.Sc. in Computer Engineering, Electrical Engineering, or a related discipline.Strong background in systems performance, platform architecture, or runtime behaviorSolid understanding ofmemory hierarchy and data movementin client or embedded systems (e.g., DRAM, caches, shared memory architectures). Strong knowledge of computer architecture, specifically memory hierarchy (DRAM, SRAM, cache), interconnect protocols (CXL, PCIe), and memory controllers.Experience with Machine Learning hardware acceleration and processing-in-memory (PIM) techniques.Knowledge of low-power design, given the \"power wall\" constraint.Experience working with heterogeneous compute environments (CPU, GPU, accelerators)Ability to translate low-level technical constraints intosystem-level guidance and platform strategyExperience collaborating across hardware, software, and product organizationsStrong technical communication skills, including engagement with external partnersPreferred ExperienceClient platforms (PC, mobile, embedded) rather than exclusively datacenter or HPC environmentsOn-device AI inference workloadsPower- and performance-sensitive system designPerformance analysis tools, telemetry, and data-driven evaluationPrior experience engaging withmemory or silicon vendorsin a technical or architectural capacityProgramming:Proficiency in C/C++ and scripting languages (Python) for modeling and analysis.Simulation Tools:Experience with architectural simulators (e.g., GEM5, Sniper) and performance analysis.Salary\r\nThe pay range for this role is$147,050to$230,850USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.Benefits:HP offers a comprehensive benefits package for this position, including:\r\nHealth insurance\r\nDental insurance\r\nVision insurance\r\nLong term/short term disability insurance\r\nEmployee assistance program\r\nFlexible spending account\r\nLife insurance\r\nGenerous time off policies, including;\r\n4-12 weeks fully paid parental leave based on tenure\r\n11 paid holidays\r\nAdditional flexible paid vacation and sick leave ( US benefits overview )The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.Job -\r\nEngineering\r\nSchedule -\r\nFull time\r\nShift -\r\nNo shift premium (United States of America)\r\nTravel -Relocation -\r\nEqual Opportunity Employer (EEO)-\r\nHP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).\r\nPlease be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.\r\nFor more information, review HP'sEEO Policyor read about your rights as an applicant under the law here: \" Know Your Rights: Workplace Discrimination is Illegal \"","company":"HP","rawCompany":"hp","city":"Spring","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-07-02T01:25:14.438Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1211.00","title":"Computer Systems Analysts","slug":"computer-systems-analysts"}],"industries":[{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"518210","title":"Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services","slug":"computing-infrastructure-providers-data-processing-web-hosting-and-related-services"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Systems Architect: Memory Wall Exploration","description":"This job is with HP, an inclusive employer and a member of myGwork – the largest global platform for the LGBTQ+ business community. Please do not contact the recruiter directly.\r\nSystems Architect: Memory Wall Exploration\r\nDescription -\r\nJob Summary:\r\nTheSystems Architect: Memory Wall Explorationfocuses on understanding how AI execution interacts with platform resources, particularly memory hierarchy, data movement, and shared-memory behavior across heterogeneous compute environments (CPU, GPU, AI accelerators). The architect will engage with internal teams and external partners (including memory and silicon vendors) to translate low-level technical characteristics into system-level guidance and platform strategy for HP.\r\nKey ResponsibilitiesPlatform Performance & Memory Analysis\r\nAnalyze how AI workloads interact with system resources across CPU, GPU, and AI acceleratorsEvaluate the impact ofmemory bandwidth, latency, contention, and data movementon workload performance, responsiveness, and power efficiencyCharacterize workload behavior inshared-memory systems, including interactions between foreground and background activityIdentify sources of performance variability and experience degradation under real-world multitasking scenarios.Overcome the performance bottleneck where processor speeds outpace memory bandwidth, focusing on optimizing data movement between CPUs, GPUs, and memory (DRAM, HBM, CXL).System-Level Guidance & Strategy\r\nTranslate memory and system-level constraints intoactionable guidancefor platformarchitecture, runtime, power, and performance teamsHelp define execution envelopes and tradeoffs (e.g., placement, concurrency limits, configuration sensitivity) that improve AI experience predictabilityContribute toplatform-level strategyby connecting technical constraints to user experience outcomes and product decisionsCross-Functional & Ecosystem Collaboration\r\nWork closely with platform architecture, runtime, power/thermal, and AI enablement teams within HPEngage with external ecosystem partners, including memory and silicon vendors, to:\r\nUnderstand platform capabilities, tradeoffs, and roadmap directionsEvaluate how memory technologies and configurations affect real-world AI experiencesTranslate partner insights intoHP-specific system guidance and strategic recommendationsSupport technical alignment discussionsPlatform Enablement\r\nAssist in defining internal tools, metrics, and evaluation methods for assessing AI workload behavior and memory sensitivityContribute to documentation, best practices, and internal frameworks related to system-level AI performanceHelp scale AI experiences across a diverse portfolio of devices and SKUsQualificationsEducation:M.Sc. in Computer Engineering, Electrical Engineering, or a related discipline.Strong background in systems performance, platform architecture, or runtime behaviorSolid understanding ofmemory hierarchy and data movementin client or embedded systems (e.g., DRAM, caches, shared memory architectures). Strong knowledge of computer architecture, specifically memory hierarchy (DRAM, SRAM, cache), interconnect protocols (CXL, PCIe), and memory controllers.Experience with Machine Learning hardware acceleration and processing-in-memory (PIM) techniques.Knowledge of low-power design, given the \"power wall\" constraint.Experience working with heterogeneous compute environments (CPU, GPU, accelerators)Ability to translate low-level technical constraints intosystem-level guidance and platform strategyExperience collaborating across hardware, software, and product organizationsStrong technical communication skills, including engagement with external partnersPreferred ExperienceClient platforms (PC, mobile, embedded) rather than exclusively datacenter or HPC environmentsOn-device AI inference workloadsPower- and performance-sensitive system designPerformance analysis tools, telemetry, and data-driven evaluationPrior experience engaging withmemory or silicon vendorsin a technical or architectural capacityProgramming:Proficiency in C/C++ and scripting languages (Python) for modeling and analysis.Simulation Tools:Experience with architectural simulators (e.g., GEM5, Sniper) and performance analysis.Salary\r\nThe pay range for this role is$147,050to$230,850USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.Benefits:HP offers a comprehensive benefits package for this position, including:\r\nHealth insurance\r\nDental insurance\r\nVision insurance\r\nLong term/short term disability insurance\r\nEmployee assistance program\r\nFlexible spending account\r\nLife insurance\r\nGenerous time off policies, including;\r\n4-12 weeks fully paid parental leave based on tenure\r\n11 paid holidays\r\nAdditional flexible paid vacation and sick leave ( US benefits overview )The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.Job -\r\nEngineering\r\nSchedule -\r\nFull time\r\nShift -\r\nNo shift premium (United States of America)\r\nTravel -Relocation -\r\nEqual Opportunity Employer (EEO)-\r\nHP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).\r\nPlease be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.\r\nFor more information, review HP'sEEO Policyor read about your rights as an applicant under the law here: \" Know Your Rights: Workplace Discrimination is Illegal \"","datePosted":"2026-07-02T01:25:14.438Z","dateModified":"2026-07-02T01:25:14.438Z","hiringOrganization":{"@type":"Organization","name":"HP","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Spring","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"cdd5a7bd688dc08d9618da94"},"url":"https://jobsearcher.com/jobs/cdd5a7bd688dc08d9618da94"}}