{"schemaVersion":"jobsearcher.job.v1","id":"cdc19eae1363b446e21415ff","url":"https://jobsearcher.com/jobs/cdc19eae1363b446e21415ff","canonicalUrl":"https://jobsearcher.com/jobs/cdc19eae1363b446e21415ff","title":"Principal Hardware Architect & Engineering Manager","description":"DEG Careers – Principal Hardware Architect & Engineering Manager Location: Irvine, CA\nEmployment Type: Full-time\nReports To: CEO / Executive Leadership\nRole Summary The Principal Hardware Architect & Engineering Manager is the senior technical and execution authority for DEG’s FPGA-based hardware platforms. This role combines hands‑on hardware architecture and board‑level design with direct management of the hardware and FPGA engineering function.\nThis position owns:\nHardware system architecture\nHardware ↔ FPGA integration\nEngineering execution, priorities, and delivery\nThis is not a pure people‑management role and not a layout‑only role. It is a hands‑on technical leadership position with real accountability.\nCore Responsibilities System & Hardware Architecture Define system‑level hardware architecture for PCIe, FMC/FMC+, and VPX platforms\nArchitect high‑speed data acquisition and playback systems\nSelect and qualify key technologies (FPGAs, ADCs/DACs, clocking subsystems)\nDefine PCIe Gen4/Gen5 hardware architecture and throughput strategy\nEstablish hardware design standards reused across product families\nOwn technical tradeoffs involving performance, risk, cost, and schedule\nBoard‑Level Hardware Design Own complete board designs from concept through production release\nDrive schematic capture for FPGA subsystems, high‑speed serial interfaces, memory, power and clocking\nDefine PCB stackups, routing constraints, and SI/PI requirements\nWork directly with PCB designers to ensure correct implementation\nLead board bring‑up, debug, and validation\nResolve cross‑discipline hardware issues (hardware ↔ FPGA ↔ test)\nDefine FPGA‑facing hardware architecture (JESD204 topology, clock domains, reset strategy, PCIe interfaces)\nReview FPGA designs for hardware compatibility and system correctness\nCollaborate with FPGA engineers on interface definition and partitioning\nEnsure hardware supports FPGA timing, clocking, and throughput needs\nThis role requires architectural understanding of FPGA systems, not day‑to‑day RTL development.\nDirectly manage hardware and FPGA engineers (employees and contractors)\nOwn engineering priorities, schedules, and resource allocation\nBalance new development, sustaining engineering, and customer‑driven work\nLead design reviews, release decisions, and technical risk assessments\nSet expectations for design quality, documentation, and release discipline\nCoordinate engineering work across hardware, FPGA, software, and test\nAct as the escalation point for technical and execution issues\nTechnical Leadership & External Interface Serve as the final technical authority for hardware decisions\nMentor engineers and enforce engineering standards\nInterface with customers on deep technical topics when required\nSupport proposal development and technical responses\nPreserve technical continuity across product generations\nRequired Qualifications 15+ years experience in complex digital and mixed‑signal hardware design\nProven ownership of complete board designs\nDemonstrated experience leading engineering teams or technical groups\nDeep expertise in PCIe, SERDES, JESD204B/C systems, clocking and power architecture\nWorking knowledge of FPGA architecture sufficient to guide integration\nStrong bring‑up and debug experience\nComfortable making final technical and execution decisions\nU.S. Person (citizenship or permanent residency)\nPreferred Experience AMD/Xilinx UltraScale+ or Versal platforms\nWideband ADC/DAC or Direct RF systems\nDefense or aerospace programs\nSmall‑team, high‑ownership environments\nCompetitive salary and comprehensive benefits package: Health insurance\nDental insurance\nVision insurance\nRetirement plan with employer matching.\nPaid time off\n\nExciting projects with the potential to make a significant impact in the field of electronic design.\nA collaborative and inclusive team culture that values creativity, initiative, and technical excellence.\nDelphi Engineering Group is a military and aerospace manufacturer requiring strict adherence to ITAR requirements. As a condition of employment applicants must provide proof of US Citizenship (no green cards or visas).\n\n#J-18808-Ljbffr","company":"Delphi Engineering Group","rawCompany":"delphi engineering group","city":"Irvine","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-17T03:31:40.792Z","occupations":[{"code":"11-9041.00","title":"Architectural and Engineering Managers","slug":"architectural-and-engineering-managers"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334118","title":"Computer Terminal and Other Computer Peripheral Equipment Manufacturing","slug":"computer-terminal-and-other-computer-peripheral-equipment-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Principal Hardware Architect & Engineering Manager","description":"DEG Careers – Principal Hardware Architect & Engineering Manager Location: Irvine, CA\nEmployment Type: Full-time\nReports To: CEO / Executive Leadership\nRole Summary The Principal Hardware Architect & Engineering Manager is the senior technical and execution authority for DEG’s FPGA-based hardware platforms. This role combines hands‑on hardware architecture and board‑level design with direct management of the hardware and FPGA engineering function.\nThis position owns:\nHardware system architecture\nHardware ↔ FPGA integration\nEngineering execution, priorities, and delivery\nThis is not a pure people‑management role and not a layout‑only role. It is a hands‑on technical leadership position with real accountability.\nCore Responsibilities System & Hardware Architecture Define system‑level hardware architecture for PCIe, FMC/FMC+, and VPX platforms\nArchitect high‑speed data acquisition and playback systems\nSelect and qualify key technologies (FPGAs, ADCs/DACs, clocking subsystems)\nDefine PCIe Gen4/Gen5 hardware architecture and throughput strategy\nEstablish hardware design standards reused across product families\nOwn technical tradeoffs involving performance, risk, cost, and schedule\nBoard‑Level Hardware Design Own complete board designs from concept through production release\nDrive schematic capture for FPGA subsystems, high‑speed serial interfaces, memory, power and clocking\nDefine PCB stackups, routing constraints, and SI/PI requirements\nWork directly with PCB designers to ensure correct implementation\nLead board bring‑up, debug, and validation\nResolve cross‑discipline hardware issues (hardware ↔ FPGA ↔ test)\nDefine FPGA‑facing hardware architecture (JESD204 topology, clock domains, reset strategy, PCIe interfaces)\nReview FPGA designs for hardware compatibility and system correctness\nCollaborate with FPGA engineers on interface definition and partitioning\nEnsure hardware supports FPGA timing, clocking, and throughput needs\nThis role requires architectural understanding of FPGA systems, not day‑to‑day RTL development.\nDirectly manage hardware and FPGA engineers (employees and contractors)\nOwn engineering priorities, schedules, and resource allocation\nBalance new development, sustaining engineering, and customer‑driven work\nLead design reviews, release decisions, and technical risk assessments\nSet expectations for design quality, documentation, and release discipline\nCoordinate engineering work across hardware, FPGA, software, and test\nAct as the escalation point for technical and execution issues\nTechnical Leadership & External Interface Serve as the final technical authority for hardware decisions\nMentor engineers and enforce engineering standards\nInterface with customers on deep technical topics when required\nSupport proposal development and technical responses\nPreserve technical continuity across product generations\nRequired Qualifications 15+ years experience in complex digital and mixed‑signal hardware design\nProven ownership of complete board designs\nDemonstrated experience leading engineering teams or technical groups\nDeep expertise in PCIe, SERDES, JESD204B/C systems, clocking and power architecture\nWorking knowledge of FPGA architecture sufficient to guide integration\nStrong bring‑up and debug experience\nComfortable making final technical and execution decisions\nU.S. Person (citizenship or permanent residency)\nPreferred Experience AMD/Xilinx UltraScale+ or Versal platforms\nWideband ADC/DAC or Direct RF systems\nDefense or aerospace programs\nSmall‑team, high‑ownership environments\nCompetitive salary and comprehensive benefits package: Health insurance\nDental insurance\nVision insurance\nRetirement plan with employer matching.\nPaid time off\n\nExciting projects with the potential to make a significant impact in the field of electronic design.\nA collaborative and inclusive team culture that values creativity, initiative, and technical excellence.\nDelphi Engineering Group is a military and aerospace manufacturer requiring strict adherence to ITAR requirements. As a condition of employment applicants must provide proof of US Citizenship (no green cards or visas).\n\n#J-18808-Ljbffr","datePosted":"2026-06-17T03:31:40.792Z","dateModified":"2026-06-17T03:31:40.792Z","hiringOrganization":{"@type":"Organization","name":"Delphi Engineering Group","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Irvine","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"cdc19eae1363b446e21415ff"},"url":"https://jobsearcher.com/jobs/cdc19eae1363b446e21415ff"}}