{"schemaVersion":"jobsearcher.job.v1","id":"cbfcefc90fdbff7dde85a13c","url":"https://jobsearcher.com/jobs/cbfcefc90fdbff7dde85a13c","canonicalUrl":"https://jobsearcher.com/jobs/cbfcefc90fdbff7dde85a13c","title":"Senior DFT Methodology Engineer - Equity Eligible","description":"NVIDIA is seeking a DFT Methodology Engineer in Santa Clara, CA. You will own and implement test access methodologies across cross-functional teams, shaping next-generation GPU designs with memory BIST, scan, and DFX security.\nYou will mentor junior engineers, collaborate with RTL, timing, physical design, software, bring-up and production teams, and help optimize trade-offs between cost and quality while delivering robust test solutions for multi-million gate designs.\n\n#J-18808-Ljbffr","company":"NVIDIA","rawCompany":"nvidia","city":"Brooklyn","state":"NY","isRemote":false,"isActive":false,"createdAt":"2026-09-10T03:10:20.317Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"513210","title":"Software Publishers","slug":"software-publishers"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Senior DFT Methodology Engineer - Equity Eligible","description":"NVIDIA is seeking a DFT Methodology Engineer in Santa Clara, CA. You will own and implement test access methodologies across cross-functional teams, shaping next-generation GPU designs with memory BIST, scan, and DFX security.\nYou will mentor junior engineers, collaborate with RTL, timing, physical design, software, bring-up and production teams, and help optimize trade-offs between cost and quality while delivering robust test solutions for multi-million gate designs.\n\n#J-18808-Ljbffr","datePosted":"2026-09-10T03:10:20.317Z","dateModified":"2026-09-10T03:10:20.317Z","hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brooklyn","addressRegion":"NY","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"cbfcefc90fdbff7dde85a13c"},"url":"https://jobsearcher.com/jobs/cbfcefc90fdbff7dde85a13c"}}