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About the job As a Design Verification Engineer, you will be an integral part of our mission to deliver cutting-edge cryptography processors. Own and develop formal and UVM verification methods to ensure the completeness and consistency of the design.
Full-timeExpandApply NowActive JobUpdated 15 days ago - UpvoteDownvoteShare Job
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So, if you are a Principal ASIC Design Verification Engineer with UVM and PCIe and/or CXL experience, please apply today! Job Title: Principal ASIC Design Verification Engineer - UVM, PCIe, CXL.
$240,000 a yearFull-timeExpandApply NowActive JobUpdated 24 days ago - UpvoteDownvoteShare Job
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Familiarity with writing regression tests for analog behavioral model verification. Familiarity with generating randomized vectors for analog behavioral model verification. Writing regression tests for analog behavioral model verification.
ExpandApply NowActive JobUpdated 9 days ago - UpvoteDownvoteShare Job
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Set up test plans and infrastructure for ASIC IC bring up and characterization and provide input of eval PCBA designs towards completion ASIC performance verification/characterization. Selection of key test and Silicon communication instruments/tools required to complete ASIC bring up/verification and characterization.
Full-timeExpandApply NowActive JobUpdated 18 days ago - UpvoteDownvoteShare Job
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Support performance verification, power-aware simulation, RTL/FW co-simulation, and GTL simulation. Industry experience as Design Verification Engineer. Improve and refine verification process.
$408,000 a yearFull-timeExpandApply NowActive JobUpdated 2 months ago - UpvoteDownvoteShare Job
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8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM. The charter of IP verification and validation team is to verify and validate the IP for robust functionality from functional simulation and FPGA development kit based HW validation.
$217,311 a yearFull-timeExpandApply NowActive JobUpdated 9 days ago - UpvoteDownvoteShare Job
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As a Senior Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.
$200,000 a yearFull-timeExpandApply NowActive JobUpdated 1 month ago - UpvoteDownvoteShare Job
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PHY verification group works closely with Analog and Digital design teams and Systems/DSP teams to incorporate and build models for mixed signal designs and validate the design against the system architecture and requirements and sets up the API building infrastructure and guidelines for the software/driver team.
Full-timeExpandApply NowActive JobUpdated 23 days ago - UpvoteDownvoteShare Job
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5+ years of experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Full-timeExpandApply NowActive JobUpdated 14 days ago - UpvoteDownvoteShare Job
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Design Verification engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.
Full-timeExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Partner with simulation infrastructure and test integration teams to set up automated verification workflows. Can be any autonomous vehicle not just terrestrial, we have had successful candidates from aerial vehicles, flying cars, autonomous boats, spacecraft, rovers, etc.
$250,800 a yearFull-timeExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. PHY Design Verification Engineer.
ExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Join Innophase IoT group as a hands-on PHY Verification Engineer/Lead and be responsible for Low-power WiFi, BT/BLE verification. Define, Develop, and refine hierarchical UVM testbench for verification of wireless PHY and MAC layers.
Full-timeExpandApply NowActive JobUpdated 1 month ago - UpvoteDownvoteShare Job
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Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. ○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
$190,000 a yearFull-timeExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Experienced in building new verification test benches using industry standard languages like System Verilog, UVM/OVM. As a Senior Principal Cache Coherency Subsystem Verification Engineer, you will the opportunity to work on and lead the verification of a server-class microprocessor-based Coherent Mesh interconnect subsystem.
$238,000 a yearFull-timeExpandApply NowActive JobUpdated 1 month ago
Title: verification Company: Insight Choices in Saratoga, CA
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