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The PM must be capable of self-managing and directing a team on awarded projects for electrical equipment, including working knowledge of critical power UPS, telecommunications, and switchgear batteries and power electronics (including UPS, Charger, rectifiers) and the associated component selection, system design & installation.
Full-timeExpandApply NowActive JobUpdated 23 days ago - UpvoteDownvoteShare Job
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Knowledge of SEMI standards, GEM/SECS interfaces, logic design, semiconductor fabrication processes, time series data analysis, and statistical quality control. Knowledge of electric systems, circuit design, and software development.
$142,140 a yearFull-timeExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Knowledge of standard cell and memory design, and RTL to GDS flow. Circuit Design experience for std cells and memories. Debug and resolve verilog, GLS, DFT, power management, and UPF modeling IP issues.
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As the DSP Architect at Axonne, you will be a key contributor to the next-generation physical layer/mixed-signal SOCs. You will be tasked with the design and development of DSP architectures and Signal-processing algorithms for advanced high-speed transceivers.
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Proficiency in the development and design of plasma and/or thermal CVD/ALD semiconductor reactor components (e.g., high temp wafer heaters, gas distribution showerheads, electrostatic chucks, wafer lift mechanisms, bellows, etc.
Full-timeExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Design, build, and maintain large-scale streaming data pipelines using technologies such as Apache Beam, Apache Kafka, Apache Kinesis, Google Cloud Pub/Sub, and Google Cloud DataFlow. We work with 40% of the Fortune 100 on their Digital initiatives and are known for our ability to integrate Strategy Consulting, Creative Design, and Technology at scale.
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ResponsibilitiesThe selected candidate will contribute to the production and delivery of transit design projects with a particular focus on, but not limited to Bus Rapid Transit (BRT) and Light Rail Transit (LRT) projects.
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Extensive Design Experience: A minimum of five (5) years of professional experience in graphic design, encompassing expertise in motion graphics, responsive design principles, and additional design territories such as video, photography, print, and other relevant media.
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Strong proficiency in independently developing and delivering hardware products as the responsible mechanical design engineer from cradle to grave. Perform design calculations, FEA, and trade studies for structural, thermal, and fluid systems.
$220,000 a yearFull-timeExpandApply NowActive JobUpdated 6 days ago - UpvoteDownvoteShare Job
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Solution Architecture & Design: Lead the architecture and design of Anaplan models, ensuring alignment with business objectives and scalability. We are seeking a highly skilled Anaplan Architect to lead and drive the design, development, and implementation of scalable Anaplan solutions.
$90 an hourExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM.
$304,750 a yearFull-timeExpandApply NowActive JobUpdated 1 month ago - UpvoteDownvoteShare Job
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Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Experience working across and building relationships with cross-functional design, model and emulation teams.
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Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware or similar floating point ALUs), embedded SRAM controllers, ARM/MIPS/RISC-V Architecture (Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation, etc.)
$190,000 a yearFull-timeExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Core Boot/BIOS and distributed uP development and JTag debugging, MADT, ACPI, IORT. UEFI expertise, WMI, SecureMor, ACPI, Capsule update. Core Boot/BIOS and distributed uP development and JTag debugging, MADT, ACPI, IORT.
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Keywords: UVM / ASIC /System Verilog / Verilog / Python / Perl/ RTL Design. 5+ years of ASIC design experience, RTL logic Design. Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.
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core design jobs Company: Oracle in Santa Clara, CA
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