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We are part of the world's top tier semiconductor supplier, SK hynix, offering Dynamic Random Access Memory chips (DRAM), Flash memory chips (NAND Flash) and CMOS Image Sensor (CIS) for a wide range of distinguished customers globally.
$252,010 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Experience in PCB layout design constraints for mixed/RF signal, high speed signal impedance control, memory interfaces, power distribution, heat dissipation, and optimization for EMI performance.
$90 an hourExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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10+ years experience of PCB layout design using Cadence Allegro. Knowledge of multilayer PCB layout, fabrication and assembly techniques including blind/buried vias, and microvias. Create and manage PCB documentation including fabrication and assembly packages, such as Gerber, ODB, BoM, fab, and assembly drawings.
$100 an hourExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Meta is seeking a PCB Design Engineer to join their team in Sunnyvale, CA. This role will oversee complex PCB/FPC design work for AR/VR devices. PCB Design Engineer - Sunnyvale, CA. Prepare fabrication notes, assembly notes, and all deliverables, such as Gerber files, drill charts, PCB assembly BOMs, and other PCB and assembly related documents required by PCB fabrication vendors to build circuit boards for prototypes and products.
$90 an hourExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Prefer previous experience designing dedication DMA engines, multimedia IPs (especially AI/ML applications), data storage, memory controllers, networking, image processing, interconnects, and/or low power design.
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They will partner with third-party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor. The DFT engineer will collaborate with cross-functional teams to implement cutting-edge designs in test access mechanisms, IO BIST, memory BIST, and scan compression.
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MediaTek’s advanced Memory Design team in San Jose is looking for a senior memory design engineer to define and architect memory circuits for high performance compute ASICs targeting Cloud AI, Data Center Networking, Automotive and other Enterprise ASIC applications as well as edge AI Machine Learning (ML) Accelerator SoCs.
$260,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Knowledge of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation. At European Recruitment we are working alongside a widely successful Bosch, Continental and BMW backed startup with locations in the US and Europe to help them bring on board a senior ASIC verification engineer.
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ASIC Verification Engineer- UVM / RISC-V / System Verilog. We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California on a remote basis.
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Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU’s engineering team in San Jose, California.
$262,700 a yearFull-timeExpandApply NowActive JobUpdated 5 days ago - UpvoteDownvoteShare Job
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Knowledge of standard cell and memory design, and RTL to GDS flow. Debug and resolve verilog, GLS, DFT, power management, and UPF modeling IP issues. Knowledge of standard cell and memory design, and RTL to GDS flow.
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Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware or similar floating point ALUs), embedded SRAM controllers, ARM/MIPS/RISC-V Architecture (Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation, etc.
$190,000 a yearFull-timeExpandApply NowActive JobUpdated 2 days ago - UpvoteDownvoteShare Job
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Deep knowledge of SAP HANA in-Memory Platform core technology, including architecture, landscape design, installation, upgrade, performance tuning and system integration. JD in details: Deep knowledge of SAP Basis tasks: technical planning, installations and configurations (SAP S/4 HANA, FIORI, SLT, SOLMAN, SAP Router.
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Minimum three years of comparable Executive Director level management experience in Assisted Living, Memory Care, Skilled Nursing, CCRC. Knowledge of federal, state and local regulatory requirements as they relate to licensed Assisted Living & Memory Care communities and the ability to lead & operate within these guidelines.
$155,000 a yearExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Strong experience, including drafting and prosecuting patent applications in hardware and software technologies, such as semiconductor technologies, digital circuitry, processors, memory solutions, artificial intelligence/machine learning, wired/wireless communication, and other hardware/software solutions and platforms.
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memory job in Cupertino, CA
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