{"schemaVersion":"jobsearcher.job.v1","id":"c6fa58533c6205ecfdea8f05","url":"https://jobsearcher.com/jobs/c6fa58533c6205ecfdea8f05","canonicalUrl":"https://jobsearcher.com/jobs/c6fa58533c6205ecfdea8f05","title":"Physical Design Engineer","description":"Job Role: Physical Design EngineerLocation: Austin, TX or San Jose, CA (Onsite)Employment Type: ContractJob SummaryWe are seeking an experienced Full-Chip Top-Level Physical Design Engineer with strong expertise in chip-level floorplanning, partitioning, power planning, timing constraints, and PPA optimization. The ideal candidate will have hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler and will work closely with ASIC vendors, IP partners, and block-level physical design teams.Key ResponsibilitiesOwn the full-chip top-level floorplan, including die/partition planning, macro and memory placement, and pin/port alignment across block boundaries.Define partition abutment, repeating structures, channels, and feedthrough strategies for clean block integration.Drive top-level PPA optimization across the chip hierarchy, focusing on power, performance, and area.Plan and review the top-level power grid / PDN in coordination with EM/IR sign-off activities.Develop and maintain top-level SDC constraints and timing budgets.Partition timing constraints and budgets down to individual block owners.Collaborate with ASIC vendors, IP partners, and block-level Physical Design engineers on floorplanning, partitioning, integration, and STA reviews.Identify and resolve top-level physical design issues impacting timing, congestion, power, and area.Participate in design reviews and drive physical implementation closure from top-level planning through sign-off.Required SkillsStrong experience in full-chip / top-level Physical Design.Hands-on expertise in chip-level floorplanning and partitioning.Experience with macro/memory placement and pin/port planning.Strong understanding of PPA optimization, congestion, timing, and power planning.Experience with power grid / PDN planning and EM/IR considerations.Strong knowledge of SDC, timing constraints, timing budgets, and STA.Experience working with block-level PD teams and external ASIC/IP vendors.Hands-on experience with Cadence Innovus.Experience with Synopsys Fusion Compiler is highly preferred.","company":"Codeplixai","rawCompany":"codeplixai","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-09-08T08:43:35.722Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Physical Design Engineer","description":"Job Role: Physical Design EngineerLocation: Austin, TX or San Jose, CA (Onsite)Employment Type: ContractJob SummaryWe are seeking an experienced Full-Chip Top-Level Physical Design Engineer with strong expertise in chip-level floorplanning, partitioning, power planning, timing constraints, and PPA optimization. The ideal candidate will have hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler and will work closely with ASIC vendors, IP partners, and block-level physical design teams.Key ResponsibilitiesOwn the full-chip top-level floorplan, including die/partition planning, macro and memory placement, and pin/port alignment across block boundaries.Define partition abutment, repeating structures, channels, and feedthrough strategies for clean block integration.Drive top-level PPA optimization across the chip hierarchy, focusing on power, performance, and area.Plan and review the top-level power grid / PDN in coordination with EM/IR sign-off activities.Develop and maintain top-level SDC constraints and timing budgets.Partition timing constraints and budgets down to individual block owners.Collaborate with ASIC vendors, IP partners, and block-level Physical Design engineers on floorplanning, partitioning, integration, and STA reviews.Identify and resolve top-level physical design issues impacting timing, congestion, power, and area.Participate in design reviews and drive physical implementation closure from top-level planning through sign-off.Required SkillsStrong experience in full-chip / top-level Physical Design.Hands-on expertise in chip-level floorplanning and partitioning.Experience with macro/memory placement and pin/port planning.Strong understanding of PPA optimization, congestion, timing, and power planning.Experience with power grid / PDN planning and EM/IR considerations.Strong knowledge of SDC, timing constraints, timing budgets, and STA.Experience working with block-level PD teams and external ASIC/IP vendors.Hands-on experience with Cadence Innovus.Experience with Synopsys Fusion Compiler is highly preferred.","datePosted":"2026-09-08T08:43:35.722Z","dateModified":"2026-09-08T08:43:35.722Z","hiringOrganization":{"@type":"Organization","name":"Codeplixai","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"c6fa58533c6205ecfdea8f05"},"url":"https://jobsearcher.com/jobs/c6fa58533c6205ecfdea8f05"}}